Array substrate, method for preparing array substrate, and backlight module

Patent metadata

Field	Value
Publication number	US-11894394-B2
Application number	US-202017281015-A
Country	US
Kind code	B2
Filing date	Jan 3, 2020
Priority date	Jan 3, 2020
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

An array substrate, a method for preparing the array substrate, and a backlight module are disclosed. Before electroplating a first metal layer on a pattern of a seed layer, the method further includes: forming a pattern of a compensation electrode wire electrically connected with a lead electrode on a side, where the lead electrode is formed, of a base substrate. The compensation electrode wire is at least on a second side of a wiring region, the pattern of the lead electrode is formed at a first side of the wiring region, and the first side and the second side are different sides. In the electroplating process, the lead electrode is connected with a negative pole of a power supply, the compensation electrode wire is electrically connected with the lead electrode, thus an area of an electroplating negative pole generating electric field lines is increased by utilizing the compensation electrode wire.

First claim

What is claimed is:

1. A method for preparing an array substrate, comprising:
forming a pattern of a seed layer in a wiring region of a base substrate;
forming a pattern of a lead electrode at a first side of the wiring region, the lead electrode being electrically connected with the seed layer;
forming a pattern of a blocking dam on a side, where the pattern of the seed layer is formed, of the base substrate, the pattern of the seed layer being complementary with the pattern of the blocking dam; and
electroplating a pattern of a first metal layer on the pattern of the seed layer, and when electroplating the pattern of the first metal layer, connecting the lead electrode with a negative pole of a power supply;
wherein before said electroplating the pattern of the first metal layer on the pattern of the seed layer, the method further comprises:
forming a pattern of a compensation electrode wire electrically connected with the lead electrode on a side, where the lead electrode is formed, of the base substrate;
wherein the compensation electrode wire is at least at a second side of the wiring region, and the first side and the second side are different sides of the wiring region.

2. The method according to claim 1 , wherein:
the pattern of the seed layer and the pattern of the lead electrode are formed by adopting a one-time patterning process; or
the pattern of the compensation electrode wire is formed when the pattern of the seed layer is formed; or
the pattern of the compensation electrode wire is formed when the pattern of the lead electrode is formed.

3. The method according to claim 1 , wherein the lead electrode is provided with a plurality of hollow regions.

4. The method according to claim 1 , wherein the compensation electrode wire and the lead electrode are distributed in a mode of surrounding the wiring region.

5. The method according to claim 1 , wherein the compensation electrode wire is provided with a plurality of hollow regions.

6. (Original The method according to claim 1 , wherein at least a material of a surface of the seed layer is same as a material of the first metal layer.

7. The method according to claim 1 , wherein a material of the first metal layer is copper.

8. The method according to claim 7 , wherein the seed layer comprises:
molybdenum and copper located sequentially on the base substrate; or
molybdenum alloy and copper located sequentially on the base substrate; or
titanium and copper located sequentially on the base substrate.

9. The method according to claim 1 , wherein after said electroplating the pattern of the first metal layer on the pattern of the seed layer, the method further comprises:
forming a planarization layer covering the pattern of the first metal layer;
forming a pattern of a connection wire on the planarization layer; and
binding an array of Light-Emitting Diodes (LEDs) on the connection wire, and electrically connecting the LEDs with the first metal layer by the connection wire.

10. The method according to claim 9 , wherein after said binding the array of the LEDs, the method further comprises:
removing the pattern of the compensation electrode wire and the pattern of the lead electrode.

11. An array substrate, prepared by adopting the method according to 10 claim 1 .

12. A backlight module, comprising a backlight driving circuit and the array substrate according to claim 11 .

Assignees

• Boe Technology Group Co Ltd

Inventors

• Cao Zhanfeng
• Liu Yingwei
• Wang Ke
• Zhang Guocai
• Wang Jianguo
• Liang Zhiwei
• Li Haixu
• Di Muxin

Classifications

• H10W90/00

  Package configurations · CPC title

• H10D86/0221

  comprising manufacture, treatment or patterning of TFT semiconductor bodies · CPC title

• H10D86/441

  Interconnections, e.g. scanning lines · CPC title

• H10H29/142

  Two-dimensional arrangements, e.g. asymmetric LED layout · CPC title

• H10H20/857

  Interconnections, e.g. lead-frames, bond wires or solder balls · CPC title