Semiconductor device including lead with varying thickness

Patent metadata

Field	Value
Publication number	US-11894281-B2
Application number	US-202117370596-A
Country	US
Kind code	B2
Filing date	Jul 8, 2021
Priority date	Sep 5, 2018
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

A semiconductor device includes a semiconductor element, a first lead electrically connected to the semiconductor element, a sealing resin that covers the semiconductor element and a part of the first lead, and a recess formed in a surface flush with a back surface of the sealing resin. The sealing resin also has a front surface opposite to the back surface in a thickness direction, and a side surface connecting the front surface and the back surface to each other. The recess is formed, in part, by a part of the first lead that is exposed from the back surface of the sealing resin. The recess has an outer edge that forms a closed shape, as viewed in the thickness direction, within a region that includes the back surface of the sealing resin and the first lead.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor chip;
at least one lead electrically connected to the semiconductor chip;
a sealing resin that covers the semiconductor chip and a part of the lead, the sealing resin including a resin front surface and a resin back surface opposite to the resin front surface in a thickness direction; and
an island portion on which the semiconductor chip is mounted,
wherein the lead includes an end portion formed with a cut-out recessed inward in plan view, while also including a thin-walled portion that is smaller in thickness than a remaining portion of the lead,
wherein the lead includes an upper surface, the end portion of the lead includes a first lower surface, and the thin-walled portion of the lead includes a second lower surface, the second lower surface being offset toward the upper surface of the lead with respect to the first lower surface,
wherein the cut-out is at least partially round in plan view, and
wherein the sealing resin comprises a first resin side surface, a second resin side surface and a third resin side surface each of which is connected to the resin front surface and the resin back surface, and the island portion is formed with a plurality of protrusions each protruding outward from one of the first, second and third resin side surfaces in plan view.

2. The semiconductor device according to claim 1 , wherein the semiconductor chip is provided with a control electrode and an output electrode, and the at least one lead comprises a first lead and a second lead, the first lead being electrically connected to the control electrode, the second lead being electrically connected to the output electrode.

3. The semiconductor device according to claim 2 , further comprising a wire that electrically connects the control electrode of the semiconductor chip to the first lead.

4. The semiconductor device according to claim 3 , further comprising an electroconductive path that electrically connects the output electrode of the semiconductor chip to the second lead, wherein the electroconductive path is smaller in resistance than the wire.

5. The semiconductor device according to claim 4 , wherein each of the first, second and third resin side surfaces is inclined with respect to the thickness direction.

6. The semiconductor device according to claim 5 , wherein the first lower surface of the end portion of the lead is formed with a recess having an outer edge that forms a closed shape in plan view.

7. The semiconductor device according to claim 6 , wherein the recess is circular in plan view.

8. The semiconductor device according to claim 7 , further comprising an additional recess spaced apart from the recess formed in the first lower surface, wherein the additional recess is defined by a part of the end portion of the lead, a part of the thin-walled portion of the lead and a part of the sealing resin.

9. The semiconductor device according to claim 8 , wherein the additional recess is rectangular in plan view.

10. The semiconductor device according to claim 9 , wherein the first lower surface of the end portion of the lead is flush with the resin back surface.

11. The semiconductor device according to claim 10 , wherein the cut-out extending in the thickness direction.

12. The semiconductor device according to claim 11 , further comprising a plating layer formed in at least a part of the cut-out.

13. The semiconductor device according to claim 2 , wherein the first lead and the second lead comprise respective inner ends that face a same side of the island portion.

14. The semiconductor device according to claim 13 , wherein the semiconductor chip is provided with an input electrode opposite to the output electrode in the thickness direction, the input electrode being electrically connected to the island portion.

15. The semiconductor device according to claim 14 , wherein the semiconductor chip comprises a transistor.

16. The semiconductor device according to claim 15 , wherein the electroconductive path comprises a plurality of wires each of which is bonded at an end to the output electrode of the semiconductor chip and bonded at an opposite end to the second lead.

17. The semiconductor device according to claim 16 , wherein the output electrode is greater in area than the control electrode in plan view.

Assignees

• Rohm Co Ltd

Inventors

• Majima Ryota
• Saito Koshun

Classifications

• H10W70/465

  Bumps or wires · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W74/127

  characterised by arrangements for sealing or adhesion · CPC title

• H10W90/756

  between a chip and a stacked lead frame, conducting package substrate or heat sink · CPC title

• H10W72/5475

  multiple bond wires connected to common bond pads at both ends of the wires · CPC title