Memory with error checking and correcting unit

Patent metadata

Field	Value
Publication number	US-11894089-B2
Application number	US-202117481413-A
Country	US
Kind code	B2
Filing date	Sep 22, 2021
Priority date	Sep 18, 2020
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

A memory is provided. The memory includes banks, each bank includes a U half bank and a V half bank; a first error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of output data of the U half banks and the V half banks; and a second error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of the output data of the U half banks and the V half banks.

First claim

The invention claimed is:

1. A memory, comprising banks, each of the banks comprising a U half bank and a V half bank;
a first error checking and correcting unit connected with U half banks and V half banks and configured to check and correct errors of output data of the U half banks and the V half banks; and
a second error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of output data of the U half banks and the V half banks;
wherein each of the U half banks comprises an even number of block data buses, and the block data buses are sequentially numbered from zero according to natural numbers;
wherein odd-numbered block data buses are connected with the first error checking and correcting unit, and even-numbered block data buses are connected with the second error checking and correcting unit; or the odd-numbered block data buses are connected with the second error checking and correcting unit, and the even-numbered block data buses are connected with the first error checking and correcting unit.

2. The memory of claim 1 , wherein the first error checking and correcting unit has a same number of input bits as the second error checking and correcting unit.

3. The memory of claim 1 , wherein the first error checking and correcting unit has a same internal error checking algorithm as the second error checking and correcting unit.

4. The memory of claim 1 , wherein the U half bank has a same storage capacity as the V half bank.

5. The memory of claim 1 , wherein each of the V half banks comprises local switch circuits and an even number of local data buses and each of the U half banks comprises local switch circuits and an even number of local data buses, the local data buses are divided into local data buses O and local data buses E, the local data buses O are connected with respective odd-numbered block data buses through respective local switch circuits, and the local data buses E are connected with respective even-numbered block data buses-E through respective local switch circuits.

6. The memory of claim 5 , wherein each local data bus is connected with an even number of sensitive amplifiers through gating switches, and the sensitive amplifiers and bit lines in the memory are disposed with one-to-one correspondence.

7. The memory of claim 6 , wherein output data on two adjacent bit lines enter the local data buses O and the local data buses E through the sensitive amplifiers and the gating switches respectively.

8. The memory of claim 7 , wherein a number of the block data buses is 2*4*(16*N), a number of the local data buses is 2*4*M*(16*N); a number of the odd-numbered block data buses is 4*(16*N), a number of the even-numbered block data buses is 4*(16*N); a number of the local data buses O is 4*M*(16*N), a number of the local data buses E is 4*M*(16*N); one block data bus O corresponds to M local data buses O, one block data bus E corresponds to M local data buses E; and the local data buses are divided into M*(16*N) groups of local data buses O and M*(16*N) groups of local data buses E by taking 4 adjacent local data buses as one group.

9. The memory of claim 1 , wherein output data of each of the U half banks comprises high bit data and low bit data; and output data of each of the V half banks comprises high bit data and low bit data.

10. A memory, comprising banks, each of the banks comprising a U half bank and a V half bank;
a first error checking and correcting unit connected with U half banks and V half banks and configured to check and correct errors of output data of the U half banks and the V half banks; and
a second error checking and correcting unit connected with the U half banks and the V half banks and configured to check and correct errors of output data of the U half banks and the V half banks;
wherein each of the V half banks comprises an even number of block data buses, and the block data buses are sequentially numbered from zero according to natural numbers;
wherein odd-numbered block data buses are connected with the first error checking and correcting unit, and even-numbered block data buses are connected with the second error checking and correcting unit; or the odd-numbered block data buses are connected with the second error checking and correcting unit, and the even-numbered block data buses are connected with the first error checking and correcting unit.

11. The memory of claim 10 , wherein the first error checking and correcting unit has a same number of input bits as the second error checking and correcting unit.

12. The memory of claim 10 , wherein the first error checking and correcting unit has a same internal error checking algorithm as the second error checking and correcting unit.

13. The memory of claim 10 , wherein the U half bank has a same storage capacity as the V half bank.

14. The memory of claim 10 , wherein each of the V half banks comprises local switch circuits and an even number of local data buses and each of the U half banks comprises local switch circuits and an even number of local data buses, the local data buses are divided into local data buses O and local data buses E, the local data buses O are connected with respective odd-numbered block data buses through respective local switch circuits, and the local data buses E are connected with respective even-numbered block data buses through respective local switch circuits.

15. The memory of claim 14 , wherein each local data bus is connected with an even number of sensitive amplifiers through gating switches, and the sensitive amplifiers and bit lines in the memory are disposed with one-to-one correspondence.

16. The memory of claim 15 , wherein output data on two adjacent bit lines enter the local data buses O and the local data buses E through the sensitive amplifiers and the gating switches respectively.

17. The memory of claim 16 , wherein a number of the block data buses is 2*4*(16*N), a number of the local data buses is 2*4*M*(16*N); a number of the odd-numbered block data buses is 4*(16*N), a number of the even-numbered block data buses is 4*(16*N); a number of the local data buses O is 4*M*(16*N), a number of the local data buses E is 4*M*(16*N); one block data bus O corresponds to M local data buses O, one block data bus E corresponds to M local data buses E; and the local data buses are divided into M*(16*N) groups of local data buses O and M*(16*N) groups of local data buses E by taking 4 adjacent local data buses as one group.

18. The memory of claim 10 , wherein output data of each of the U half banks comprises high bit data and low bit data; and output data of each of the V half banks comprises high bit data and low bit data.

Assignees

• Changxin Memory Tech Inc

Inventors

• Shang Weibing
• Li Hongwen
• Zhang Liang
• Ji Kangling
• Chi Sungsoo
• Wu Daoxun
• Wang Ying

Classifications

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title

• G11C29/026

  in sense amplifiers · CPC title

• G11C29/10

  Test algorithms, e.g. memory scan [MScan] algorithms; Test patterns, e.g. checkerboard patterns · CPC title

• G11C29/4401

  for self repair · CPC title

• G11C2029/1204

  Bit line control · CPC title