Anti-fuse memory and control method thereof

Patent metadata

Field	Value
Publication number	US-11894082-B2
Application number	US-202217712070-A
Country	US
Kind code	B2
Filing date	Apr 2, 2022
Priority date	Dec 24, 2021
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

Embodiments of the present disclosure relate to the field of semiconductor technology, and provide an anti-fuse memory and a control method thereof. The anti-fuse memory is configured to generate a programming pulse signal based on a row strobe signal, a word line of the anti-fuse memory array is configured to receive the row strobe signal, and the anti-fuse memory array is programmed in response to the programming pulse signal. The embodiments of the present disclosure are at least advantageous to improving accuracy of reading data from the anti-fuse memory array and improving yield of the anti-fuse memory.

First claim

What is claimed is:

1. An anti-fuse memory configured to generate a programming pulse signal based on a row strobe signal, a word line of the anti-fuse memory being configured to receive the row strobe signal, and the anti-fuse memory being programmed in response to the programming pulse signal;
wherein the anti-fuse memory is further configured to generate the programming pulse signal with an adjustable duty factor based on the row strobe signal.

2. The anti-fuse memory according to claim 1 , wherein the anti-fuse memory is further configured to generate the programming pulse signal based on the row strobe signal and a reference pulse signal.

3. The anti-fuse memory according to claim 2 , wherein the reference pulse signal is an internal clock signal.

4. The anti-fuse memory according to claim 2 , wherein the anti-fuse memory comprises a reference pulse signal generation module configured to output the reference pulse signal with the adjustable duty factor.

5. The anti-fuse memory according to claim 1 , wherein the anti-fuse memory comprises a pulse signal generation module configured to receive the row strobe signal and generate the programming pulse signal.

6. The anti-fuse memory according to claim 5 , wherein the pulse signal generation module comprises:
a signal generation unit configured to output an initial pulse signal in response to the row strobe signal; and
a level translator configured to perform level translation on the initial pulse signal to generate and output the programming pulse signal, a level value of the programming pulse signal being greater than that of the initial pulse signal.

7. The anti-fuse memory according to claim 6 , wherein the signal generation unit is configured to output the initial pulse signal in response to the row strobe signal and a reference pulse signal simultaneously.

8. The anti-fuse memory according to claim 7 , wherein the reference pulse signal has an adjustable duty factor.

9. The anti-fuse memory according to claim 6 , wherein the signal generation unit comprises a ring oscillator circuit, the row strobe signal being an enable signal of the ring oscillator circuit, and an output terminal of the ring oscillator circuit being configured to output the initial pulse signal.

10. The anti-fuse memory according to claim 9 , wherein the ring oscillator circuit is configured to output the initial pulse signal with an adjustable duty factor.

11. The anti-fuse memory according to claim 10 , wherein the ring oscillator circuit comprises:
a comparison circuit, an output terminal of the comparison circuit being configured to output the initial pulse signal;
a pull-up module connected between an operating power source and an input terminal of the comparison circuit, the pull-up module being enabled in response to the row strobe signal and a first level signal outputted from the comparison circuit and being configured to pull up a voltage across the input terminal of the comparison circuit at a first speed, the first speed being adjustable; and
a pull-down module connected between a ground terminal and the input terminal of the comparison circuit, the pull-down module being enabled in response to the row strobe signal and a second level signal outputted from the comparison circuit and being configured to pull down the voltage across the input terminal of the comparison circuit at a second speed, the second speed being adjustable, and a level value of the first level signal being different from that of the second level signal.

12. The anti-fuse memory according to claim 11 , wherein the pull-up module comprises a first current source and a first switch module, the first switch module being connected between the first current source and the input terminal of the comparison circuit, and the first switch module being enabled in response to the row strobe signal and the first level signal; and
the pull-down module comprises a second current source and a second switch module, the second switch module being connected between the second current source and the input terminal of the comparison circuit, and the second switch module being enabled in response to the row strobe signal and the second level signal, and the first current source and/or the second current source being adjustable in magnitude of current.

13. The anti-fuse memory according to claim 12 , wherein the comparison circuit comprises a comparator and a second inverter connected in series with the comparator, an output terminal of the second inverter being configured to output the initial pulse signal;
the first switch module comprises a first switch transistor and a second switch transistor connected in series, the first current source being connected between the first switch transistor and the operating power source, a control terminal of the second switch transistor being connected to the output terminal of the second inverter, and the first switch transistor being enabled in response to the row strobe signal; and
the second switch module comprises a third switch transistor and a fourth switch transistor connected in series, the second current source being connected between the fourth switch transistor and the ground terminal, a control terminal of the third switch transistor being connected to the output terminal of the second inverter, and the fourth switch transistor being enabled in response to the row strobe signal.

14. The anti-fuse memory according to claim 12 , wherein the anti-fuse memory further comprises a current adjustment module configured to adjust magnitude of current of the first current source and/or the second current source.

15. A control method for an anti-fuse memory, the control method comprising:
generating a programming pulse signal in response to a row strobe signal; and
programming in response to the programming pulse signal;
wherein the generating a programming pulse signal in response to the row strobe signal comprises: generating the programming pulse signal in response to the row strobe signal and a reference pulse signal simultaneously, the reference pulse signal having an adjustable duty factor.

16. The control method according to claim 15 , wherein the generating a programming pulse signal in response to the row strobe signal comprises: generating the programming pulse signal having an adjustable duty factor in response to the row strobe signal.

Assignees

• Changxin Memory Tech Inc

Inventors

• Ji Rumin

Classifications

• H10W20/491 Primary

  Antifuses, i.e. interconnections changeable from non-conductive to conductive · CPC title

• H10B20/20

  Programmable ROM [PROM] devices comprising field-effect components (H10B20/10 takes precedence) · CPC title

• G11C17/165 Primary

  Memory cells which are electrically programmed to cause a change in resistance, e.g. to permit multiple resistance steps to be programmed rather than conduct to or from non-conduct change of fuses and antifuses (digital stores using resistance random access memory elements G11C13/0002) · CPC title

• G11C17/18

  Auxiliary circuits, e.g. for writing into memory · CPC title

• H01L23/5252

  Electricity · mapped topic