Non-volatile memory programming circuit and a method of programming non-volatile memory devices

Patent metadata

Field	Value
Publication number	US-11894061-B2
Application number	US-202217733877-A
Country	US
Kind code	B2
Filing date	Apr 29, 2022
Priority date	May 19, 2021
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

A memory programming circuit for programming a non-volatile memory device having an array structure includes a plurality of rows, each row having a row index and comprising one or more memory units, each memory unit being configured to receive one or more input signals and to deliver one or more output signals, the memory programming circuit comprising: a first source line connected to the top electrode of the memory units comprised at rows of odd row indices, and a second source line connected to the top electrodes of the memory units comprised at rows of even row indices.

First claim

The invention claimed is:

1. A non-volatile memory device comprising a memory programming circuit for programming said non-volatile memory device, said non-volatile memory device having an array structure comprising a plurality of rows of a given number, each row having a row index varying from one to said given number and comprising one or more memory units, each memory unit being configured to receive one or more input signals and to deliver one or more output signals, wherein the memory programming circuit comprises:
a plurality of first source lines connected to the top electrode of the memory units comprised at rows of odd row indices, and;
a plurality of second source lines connected to the top electrodes of the memory units comprised at rows of even row indices;
an analog circuit configured to receive the output signals delivered by said one or more memory units and to deliver to at least one memory unit a programming signal as an input signal, said analog circuit being configured to perform a programming operation for each pair of successive rows in said plurality of rows, a pair of successive rows comprising a first row and a second row, the first row being connected to a first line selected among said plurality of first source lines and said plurality of second source lines depending on whether the row index of said first row is odd or even, the second row being connected to a second line selected among said plurality of first source lines and said plurality of second source lines depending on whether the row index of said second row is odd or even, the analog circuit being configured to perform said programming operation by:
reading the output signal or signals delivered by the memory units comprised in said first row;
applying a read voltage to said first line;
determining a programming signal by applying a signal transformation function to said output signals;
applying a programming voltage to said second line, and
feeding the memory units comprised in said second row by said programming signal as the input signal of each of said memory units.

2. The non-volatile memory device of claim 1 , wherein said analog circuit is a single circuit multiplexed between said plurality of rows, said analog circuit comprising a multiplexer, a signal transforming unit, and a de-multiplexer, said multiplexer being configured to receive the output signals delivered by the one or more memory units comprised in said plurality of rows, said signal transforming unit being configured to perform said programming operation, and said de-multiplexer being configured to feed each programming signal to the memory units comprised in the appropriate row.

3. The non-volatile memory device of claim 1 , wherein the signal transformation function is a current multiplication function, said output signal being a current signal, the analog circuit being a current buffer amplifier configured to apply a virtual ground, read said current signal and determine said programming signal as a voltage signal.

4. The non-volatile memory device of claim 3 , wherein said analog circuit comprising a resistor-divider configured to determine said voltage signal from the read current.

5. The non-volatile memory device of claim 1 , wherein the signal transformation function is a square root function.

6. The non-volatile memory device of claim 1 , wherein the signal transformation function is a voltage multiplication function.

7. The non-volatile memory device of claim 1 , wherein said non-volatile memory device is chosen in a group of non-volatile memory devices comprising phase change memory devices, ferroelectric random access memory devices, ferromagnetic field effect transistors, FLASH transistors, and resistive memory devices, said resistive memory devices comprising magneto-resistive random access memory devices and resistive switching random access memory devices.

8. A method for programming a non-volatile memory device, said non-volatile memory device having an array structure comprising a plurality of rows of a given number, each row having a row index varying from one to said given number and comprising one or more memory units, each memory unit receiving one or more input signals and delivering one or more output signals, wherein the method comprises:
connecting a plurality of first source lines to the top electrode of the memory units comprised at rows of odd row indices, and
connecting a plurality of second source lines to the top electrodes of the memory units comprised at rows of even row indices;
performing a programming operation by an analog circuit for each pair of successive rows in said plurality of rows, a pair of successive rows comprising a first row and a second row, the first row being connected to a first line selected among said first source line and said second source line depending on whether the row index of said first row is odd or even, the second row being connected to a second line selected among said first source line and second source line depending on whether the row index of said second row if odd or even, said programming operation comprising:
reading the output signals delivered by the memory units comprised in said first row;
applying a read voltage to the first line;
determining a programming signal from said output signals by applying a signal transformation function;
applying a programming voltage to said second line, and
feeding the memory units comprised in said second row by said programming signal as the input.

Assignees

• Commissariat Energie Atomique

Inventors

• Dalgaty Thomas

Classifications

• G06N3/092

  Reinforcement learning · CPC title

• G11C16/102 Primary

  External programming circuits, e.g. EPROM programmers; In-circuit programming or reprogramming; EPROM emulators · CPC title

• G11C7/1012

  Data reordering during input/output, e.g. crossbars, layers of multiplexers, shifting or rotating · CPC title

• G11C16/0433

  comprising cells containing a single floating gate transistor and one or more separate select transistors · CPC title

• G11C16/26

  Sensing or reading circuits; Data output circuits · CPC title