Vertical nonvolatile memory device including memory cell string

Patent metadata

Field	Value
Publication number	US-11894053-B2
Application number	US-202318156543-A
Country	US
Kind code	B2
Filing date	Jan 19, 2023
Priority date	Jan 14, 2020
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

A vertical nonvolatile memory device including a memory cell string using a resistance change material is disclosed. Each memory cell string of the nonvolatile memory device includes a semiconductor layer extending in a first direction and having a first surface opposite a second surface, a plurality of gates and a plurality of insulators alternately arranged in the first direction and extending in a second direction perpendicular to the first direction, a gate insulating layer extending in the first direction between the plurality of gates and the semiconductor layer and between the plurality of insulators and the semiconductor layer, and a dielectric film extending in the first direction on the surface of the semiconductor layer and having a plurality of movable oxygen vacancies distributed therein.

First claim

What is claimed is:

1. A nonvolatile memory device comprising:
a plurality of memory cell strings that each include
a semiconductor layer extending in a first direction and having a first surface opposite a second surface,
a plurality of gates and a plurality of insulators extending in a second direction perpendicular to the first direction, the plurality of gates and the plurality of insulators being alternately arranged in the first direction,
a gate insulating layer extending in the first direction between the plurality of gates and the first surface of the semiconductor layer and between the plurality of insulators and the first surface of the semiconductor layer, and
a dielectric film extending in the first direction on the second surface of the semiconductor layer, the dielectric film including a mixture of a material of the semiconductor layer and a transition metal oxide.

2. The nonvolatile memory device of claim 1 , wherein a material of the semiconductor layer includes at least one of Si, Ge, indium gallium zinc oxide (IGZO), and GaAs, and
wherein the transition metal oxide includes an oxide of at least one of zirconium (Zr), hafnium (Hf), aluminum (Al), nickel (Ni), copper (Cu), molybdenum (Mo), tantalum (Ta), titanium (Ti), tungsten (W), chromium (Cr), strontium (Sr), lanthanum (La), manganese (Mn), calcium (Ca), and praseodymium (Pr).

3. The nonvolatile memory device of claim 1 , wherein a proportion of the material of the semiconductor layer in the dielectric film is about 20 at. % to about 80 at. %.

4. The nonvolatile memory device of claim 3 , wherein the proportion of the material of the semiconductor layer in the dielectric film is about 40 at. % to about 60 at. %.

5. The nonvolatile memory device of claim 3 , wherein the proportion of the material of the semiconductor layer in the dielectric film is constant within a deviation range of about 10% in an entire region of the dielectric film.

6. The nonvolatile memory device of claim 1 ,
wherein a width of the dielectric film in the second direction is about 1.5 nm to about 10 nm, and
wherein the width of the dielectric film is constant within a deviation range of about 10% in an entire region of the dielectric film.

7. The nonvolatile memory device of claim 1 , wherein
the dielectric film includes a plurality of first layers and plurality of second layers,
the plurality of first layers are formed of the material of the semiconductor layer, the plurality of second layers are formed of the transition metal oxide, and
the plurality of first layers and the plurality of second layers are alternately arranged in the first direction.

8. The nonvolatile memory device of claim 7 , wherein
a thickness of each of the plurality of first layers and a thickness of each of the plurality of second layers are about 0.1 nm to about 1 nm, and
a ratio of the thickness of each of the plurality of first layers to a sum of thicknesses of each of the plurality of first layers and each of the plurality of second layers is constant within a deviation range of about 10% in an entire region of the dielectric film.

9. The nonvolatile memory device of claim 8 , wherein the ratio of the thickness of each of the plurality of first layers to a sum of the thicknesses of each of the plurality of first layers and each of the plurality of second layers is about 20% to about 80%.

10. The nonvolatile memory device of claim 9 , wherein the ratio of the thickness of each of the plurality of first layers to the sum of the thicknesses of each of the plurality of first layers and each of the plurality of second layers is about 40% to about 60%.

11. The nonvolatile memory device of claim 1 , wherein
each of the plurality of memory cell strings further includes a resistance change layer,
the resistance change layer faces the second surface of the semiconductor layer,
the resistance change layer extends in the first direction, and
the dielectric film is between the second surface of the semiconductor layer and the resistance change layer.

12. The nonvolatile memory device of claim 11 , wherein the dielectric film includes a mixture of the material of the semiconductor layer and a material of the resistance change layer.

13. The nonvolatile memory device of claim 12 , wherein
each corresponding memory cell string of the plurality of memory cell strings includes a plurality of memory cells arranged in a vertical stacked structure of the corresponding memory cell string, and
each corresponding memory cell of the plurality of memory cells in the corresponding memory cell string is defined by
a corresponding gate among the plurality of gates in the corresponding memory cell, a part of the semiconductor layer of the corresponding memory cell string adjacent to the corresponding gate in the second direction,
a part of the gate insulating layer of the corresponding memory cell string adjacent to the corresponding gate in the second direction,
a part of the dielectric film of the corresponding memory cell string adjacent to the corresponding gate in the second direction, and
a part of the resistance change layer of the corresponding memory cell string adjacent to the corresponding gate in the second direction.

14. The nonvolatile memory device of claim 13 , further comprising:
a control logic configured to control voltages applied to at least one of the plurality of memory cell strings such that, during a read mode,
the control logic is configured to apply a first voltage to an unselected memory cell for causing a current to flow only through the semiconductor layer of the unselected memory cell, and
the control logic being configured to apply a second voltage to a selected memory cell for causing a current to flow through all of the semiconductor layer, the dielectric film, and the resistance change layer of the selected memory cell; and
a bit line configured to apply a read voltage to the selected memory cell, wherein
the unselected memory cell and the selected memory cell are among the plurality of memory cells in the plurality of memory cell strings, and
the selected memory cell is in a selected memory cell string among the plurality of memory cell strings, and

wherein an absolute value of the second voltage is less than an absolute value of the first voltage.

15. The nonvolatile memory device of claim 14 , wherein
the second voltage has a value that causes a resistance of the semiconductor layer of the selected memory cell to be greater than or equal to a minimum resistance of a combined resistance of a resistance of the dielectric film and a resistance of the resistance change layer of the selected memory cell.

16. The nonvolatile memory device of claim 14 , wherein the second voltage has a value that causes a resistance of the semiconductor layer of the selected memory cell to be less than or equal to a maximum resistance of a combined resistance of a resistance of the dielectric film and a resistance of the resistance change layer of the selected memory cell.

17. The nonvolatile memory device of claim 14 , wherein
the absolute value of the second voltage is greater than an absolute value of a third voltage, and
the control logic is configured to apply the third voltage to the selected memory cell for causing a current to flow through only the dielectric film and the resistance change layer of the selected memory cell in the selected memory cell string.

18. The nonvolatile memory device of claim 17 , wherein
the control logic is configured to control voltages applied to at least one of the

Assignees

• Samsung Electronics Co Ltd

Inventors

• Cho Youngjin
• Yoon Jungho
• Kim Seyun
• Kim Jinhong
• Mizusaki Soichiro

Classifications

• H10D30/69

  IGFETs having charge trapping gate insulators, e.g. MNOS transistors · CPC title

• H10D30/0413

  of FETs having charge-trapping gate insulators, e.g. MNOS transistors · CPC title

• G11C13/0069 Primary

  Writing or programming circuits or methods · CPC title

• G06N3/04

  Architecture, e.g. interconnection topology · CPC title

• G11C13/004

  Reading or sensing circuits or methods · CPC title