Gate driving circuit and display panel that alleviate trailing of a falling edge of a signal output terminal

Patent metadata

Field	Value
Publication number	US-11893919-B2
Application number	US-202117765373-A
Country	US
Kind code	B2
Filing date	Jun 10, 2021
Priority date	Jul 31, 2020
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

A gate driving circuit and a display panel are provided. The gate driving circuit includes M shift registers and N clock signal lines; every N adjacent shift registers among the M shift registers are respectively connected to the N clock signal lines, where N is an even number greater than or equal to 4, and M is an integer greater than or equal to N; a signal output terminal (OUTPUT) of an i th shift register is connected to a signal input terminal (INPUT) of a (i+p) th shift register, where (N−4)/2≤p≤N/2, and i is taken from 1 to (M−p); and a pull-up reset signal terminal of a j th shift register is connected to a signal output terminal (OUTPUT) of a (j+q) th shift register, where 1<q−p<N/2, and j is taken from 1 to (M−q).

First claim

What is claimed is:

1. A gate driving circuit, comprising M shift registers and N clock signal lines; every N adjacent shift registers among the M shift registers being respectively connected to the N clock signal lines, where N is an even number greater than, and M is an integer greater than or equal to N;
wherein each of the M shift registers at least comprises an input sub-circuit, an output sub-circuit and a pull-up reset sub-circuit; in response to an input signal input by a signal input terminal, the input sub-circuit writes the input signal into a pull-up node; in response to a potential of the pull-up node, the output sub-circuit outputs a clock signal input by a clock signal terminal through a signal output terminal; and in response to a pull-up reset signal input by a pull-up reset signal terminal, the pull-up reset sub-circuit resets the potential of the pull-up node through a turn-off level signal;
a signal output terminal of an i th shift register is connected to a signal input terminal of a (i+p) th shift register, where (N−4)/2≤p≤N/2, and i is taken from 1 to (M−p);
a pull-up reset signal terminal of a j th shift register is connected to a signal output terminal of a (j+q) th shift register, where 1<q−p<N/2, and j is taken from 1 to (M−q);
wherein each of the shift registers further comprises an output reset sub-circuit and in response to an output reset signal input by an output reset signal terminal, the output reset sub-circuit resets the signal output terminal through the turn-off level signal;
wherein an output reset signal terminal of a k th shift register is connected to a signal output terminal of a (k+p) th shift register, where k is taken from 1 to (M−p);
wherein the output reset signal terminal is configured to reset only the signal output terminal; and
wherein the output sub-circuit is configured to operate for a delay of ⅖ of one period of the clock signal.

2. The gate driving circuit of claim 1 , wherein p=(N−4)/2 in a case where a duty ratio of the clock signal is 30% and N≥6.

3. The gate driving circuit of claim 2 , wherein signal input terminals of a first to a ((N−4)/2) th shift registers respond to a frame start signal;
the gate driving circuit further comprises 2q redundant shift registers, and every N adjacent redundant shift registers among the 2q redundant shift registers are respectively connected to the N clock signal lines;
signal output terminals of a first to a q th redundant shift registers are respectively connected to pull-up reset signal terminals of a (M−q+1) th to an M th shift registers;
signal output terminals of a (q+1) th to a (2q) th redundant shift registers are respectively connected to pull-up reset signal terminals of the first to the q th redundant shift registers; and
signal output terminals of a (M−(N−6)/2) th to the M th shift registers are respectively connected to signal input terminals of the first to a ((N−4)/2) th redundant shift registers; and a signal output terminal of an h th redundant shift register is connected to a signal input terminal of a (h+(N−4)/2) th redundant shift register; where h is taken from 1 to (2q−(N−4)/2).

4. The gate driving circuit of claim 1 , wherein p=(N−2)/2 in a case where a duty ratio of the clock signal is 40% and N>4.

5. The gate driving circuit of claim 4 , wherein signal input terminals of a first to a ((N−2)/2) th shift registers respond to a frame start signal;
the gate driving circuit further comprises 2q redundant shift registers, and every N adjacent redundant shift registers among the 2q redundant shift registers are respectively connected to the N clock signal lines;
signal output terminals of a first to a q th redundant shift registers are respectively connected to pull-up reset signal terminals of a (M−q+1) th to an M th shift registers;
signal output terminals of a (q+1) th to a (2q) th redundant shift registers are respectively connected to pull-up reset signal terminals of the first to the q th redundant shift registers; and
signal output terminals of a (M−(N−4)/2) th to the M th shift registers are respectively connected to signal input terminals of the first to a ((N−2)/2) th redundant shift registers; and a signal output terminal of an h th redundant shift register is connected to a signal input terminal of a (h+(N−2)/2) th redundant shift register; where h is taken from 1 to (2q−(N−2)/2).

6. The gate driving circuit of claim 1 , wherein p=N/2 in a case where a duty ratio of the clock signal is 50% and N>4.

7. The gate driving circuit of claim 6 , wherein signal input terminals of a first to a N/2 th shift registers respond to a frame start signal;
the gate driving circuit further comprises 2q redundant shift registers, and every N adjacent redundant shift registers among the 2q redundant shift registers are respectively connected to the N clock signal lines;
signal output terminals of a first to a q th redundant shift registers are respectively connected to pull-up reset signal terminals of a (M−q+1) th to an M th shift registers;
signal output terminals of a (q+1) th to a (2q) th redundant shift registers are respectively connected to pull-up reset signal terminals of the first to the q th redundant shift registers; and
signal output terminals of a (M−(N−2)/2) th to the M th shift registers are respectively connected to signal input terminals of the first to a N/2 th redundant shift registers; and a signal output terminal of an h th redundant shift register is connected to a signal input terminal of a (h+N/2) th redundant shift register; where h is taken from 1 to (2q−N/2).

8. A display panel, comprising the gate driving circuit of claim 1 .

Assignees

• Beijing Boe Display Tech Co
• Boe Technology Group Co Ltd
• Beijing Boe Display Techology Co Ltd

Inventors

• Su Qiujie
• Qu Feng
• Sun Zhihua
• Lee Seungmin
• Liao Yanping
• Yue Hongli

Classifications

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2310/0286

  Details of a shift registers arranged for use in a driving circuit · CPC title