Interface and warm reset path for memory device firmware upgrades

Patent metadata

Field	Value
Publication number	US-11893379-B2
Application number	US-202016995934-A
Country	US
Kind code	B2
Filing date	Aug 18, 2020
Priority date	May 15, 2020
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

Systems, apparatuses and methods may provide for technology that exchanges activation information between system firmware and an operating system (OS), wherein the activation information includes one or more of status information, activation state information, capability information, activation time information or quiesce time information. The technology also conducts a runtime upgrade of the device firmware based on the activation information, wherein the runtime upgrade bypasses a reboot of the computing system.

First claim

We claim:

1. A computing system comprising:
a network controller;
a processor coupled to the network controller;
a memory device coupled to the processor, the memory device including device firmware; and
a system memory coupled to the processor, the system memory including a set of executable program instructions, which when executed by the processor, cause the processor to:
exchange activation information between system firmware and an operating system (OS), wherein the activation information includes one or more of status information, activation state information, capability information, activation time information or quiesce time information,
conduct a runtime upgrade of the device firmware based on the activation information, wherein the runtime upgrade bypasses a reboot of the computing system,
determine whether memory initialization code associated with the computing system supports warm resets,
activate the device firmware if the memory initialization code supports warm resets, and
invoke a microcontroller to activate the device firmware if the memory initialization code does not support warm resets, wherein the device firmware is to be activated before being executed from the memory device.

2. The computing system of claim 1 , wherein the runtime upgrade is to be conducted via a warm reset, the status information is to indicate a last firmware activation status, the activation state information is to indicate a firmware activation arm state, the capability information is to indicate a warm reset capability, the activation time information is to indicate an estimated firmware activation time, and the quiesce time information is to indicate an estimated quiesce time.

3. The computing system of claim 2 , further including the microcontroller, wherein to activate the device firmware, the instructions, when executed, further cause the processor to:
activate the device firmware with a basic input output system (BIOS).

4. The computing system of claim 3 , wherein the device firmware is to be activated before input/output (I/O) devices are enabled to access the memory device.

5. The computing system of claim 3 , wherein the microcontroller is to quiesce the computing system, and wherein the microcontroller includes one or more of a baseboard management controller, a system management controller, a security controller or a power management controller.

6. The computing system of claim 1 , wherein the OS is to prepare to activate the device firmware with quiesce, and wherein once activation of the device firmware is completed, the OS is to re-evaluate a timer so that an OS time and a wall clock time are in sync.

7. The computing system of claim 1 , wherein the OS is to perform input/output (I/O) access to host memory quiesce by one or more of a disablement of direct memory access (DMA), a pause of I/O devices, or a hibernation of I/O devices to conduct a runtime activation of the device firmware.

8. A semiconductor apparatus comprising:
one or more substrates; and
logic coupled to the one or more substrates, wherein the logic is implemented at least partly in one or more of configurable logic or fixed-functionality hardware logic, the logic coupled to the one or more substrates to:
exchange activation information between system firmware and an operating system (OS), wherein the activation information includes one or more of status information, activation state information, capability information, activation time information or quiesce time information;
conduct a runtime upgrade of device firmware based on the activation information, wherein the runtime upgrade bypasses a reboot of a computing system;
determine whether memory initialization code associated with the computing system supports warm resets;
activate the device firmware if the memory initialization code supports warm resets; and
invoke a microcontroller to activate the device firmware if the memory initialization code does not support warm resets, wherein the device firmware is to be activated before being executed from a memory device.

9. The apparatus of claim 8 , wherein the runtime upgrade is to be conducted via a warm reset, the status information is to indicate a last firmware activation status, the activation state information is to indicate a firmware activation arm state, the capability information is to indicate a warm reset capability, the activation time information is to indicate an estimated firmware activation time, and the quiesce time information is to indicate an estimated quiesce time.

10. The apparatus of claim 9 , wherein to activate the device firmware, the logic coupled to the one or more substrates is to:
activate the device firmware with a basic input output system (BIOS).

11. The apparatus of claim 10 , wherein the device firmware is to be activated before input/output (I/O) devices are enabled to access the memory device.

12. The apparatus of claim 10 , wherein the microcontroller is to quiesce the computing system, and wherein the microcontroller is to include one or more of a baseboard management controller, a system management controller, a security controller or a power management controller.

13. The apparatus of claim 8 , wherein the OS is to prepare to activate the device firmware with quiesce, and wherein once activation of the device firmware is completed, the OS is to re-evaluate a timer so that an OS time and a wall clock time are in sync.

14. The apparatus of claim 8 , wherein the OS is to perform input/output (I/O) access to host memory quiesce by one or more of a disablement of direct memory access (DMA), a pause of I/O devices, or a hibernation of I/O devices to conduct a runtime activation of the device firmware.

15. The apparatus of claim 8 , wherein the logic coupled to the one or more substrates includes transistor channel regions that are positioned within the one or more substrates.

16. At least one computer readable storage medium comprising a set of executable program instructions, which when executed by a computing system, cause the computing system to:
exchange activation information between system firmware and an operating system (OS), wherein the activation information includes one or more of status information, activation state information, capability information, activation time information or quiesce time information;
conduct a runtime upgrade of device firmware based on the activation information, wherein the runtime upgrade bypasses a reboot of the computing system;
determine whether memory initialization code associated with the computing system supports warm resets;
activate the device firmware if the memory initialization code supports warm resets; and
invoke a microcontroller to activate the device firmware if the memory initialization code does not support warm resets, wherein the device firmware is to be activated before being executed from a memory device.

17. The at least one computer readable storage medium of claim 16 , wherein the runtime upgrade is to be conducted via a warm reset, the status information is to indicate a last firmware activation status, the activation state information is to indicate a firmware activation arm state, the capability information is to indicate a warm reset capability, the activation time information is to indicate an estimated firmware activation time, and the quiesce time information is to indicate an estimated quiesce time.

18. The at least one computer readable storage medium of claim 17 , wherein to activate the device firmware, the instructions, when executed, further cause

Assignees

• Intel Corp

Inventors

• Nachimuthu Murugasamy K
• Gandiga Shivakumar Deepak
• Williams Dan
• Kasanicky Tiffany
• Rusocki Krzysztof
• Moulin Nicholas
• Kumar Mohan J

Classifications

• G06F8/654 Primary

  using techniques specially adapted for alterable solid state memories, e.g. for EEPROM or flash memories · CPC title

• G06F8/656

  while running · CPC title

• G06F9/4401

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06F8/65 Primary

  Updates (security arrangements therefor G06F21/57) · CPC title