Integrated circuit, and digital fingerprint generation circuit and method thereof

Patent metadata

Field	Value
Publication number	US-11893142-B2
Application number	US-202117503167-A
Country	US
Kind code	B2
Filing date	Oct 15, 2021
Priority date	Dec 3, 2020
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

A digital fingerprint generation circuit based on an integrated circuit is provided. In the digital fingerprint generation circuit, a control unit is configured to: generate a first control word and a second control word, and transmit the first control word and the second control word to a first clock generator and a second clock generator respectively, so that the first clock generator generates a first clock signal based on the first control word, and the second clock generator generates a second clock signal based on the second control word; and a frequency detector generates a digital fingerprint of the integrated circuit based on the first clock signal and the second clock signal.

First claim

What is claimed is:

1. A digital fingerprint generation circuit based on an integrated circuit, comprising: a control unit, a first clock generator, a second clock generator, and a frequency detector, wherein
the control unit is electrically coupled with the first clock generator and the second clock generator, and the control unit is configured to: generate a first control word and a second control word, transmit the first control word to the first clock generator, and transmit the second control word to the second clock generator;
the first clock generator is further electrically coupled with the frequency detector, and the first clock generator is configured to: generate a first clock signal based on the first control word and transmit the first clock signal to the frequency detector;
the second clock generator is further electrically coupled with the frequency detector, and the second clock generator is configured to: generate a second clock signal based on the second control word and transmit the second clock signal to the frequency detector; and
the frequency detector is configured to generate a digital fingerprint of the integrated circuit based on the first clock signal and the second clock signal;
wherein the first clock generator and the second clock generator have different manufacturing deviations, and both of the first control word and the second control word have an integer portion and a fraction portion.

2. The digital fingerprint generation circuit according to claim 1 , wherein the frequency detector is configured to:
output a first parameter value in response to a difference between a period of the second clock signal and a period of the first clock signal being greater than or equal to a difference threshold;
output a second parameter value in response to the difference between the period of the second clock signal and the period of the first clock signal being less than the difference threshold;
wherein after a plurality of periods, the digital fingerprint of the integrated circuit is formed by at least one first parameter value and at least one second parameter value output by the frequency detector.

3. The digital fingerprint generation circuit according to claim 2 , wherein the difference threshold is 0.

4. The digital fingerprint generation circuit according to claim 2 , wherein the first parameter value is 1, and the second parameter value is 0.

5. The digital fingerprint generation circuit according to claim 2 , wherein the frequency detector comprises a D flip-flop.

6. The digital fingerprint generation circuit according to claim 2 , wherein an output of the frequency detector comprises a response to a challenge of the digital fingerprint generation circuit, wherein
the challenge of the digital fingerprint generation circuit is a set comprising the first control word, the second control word, a first initial address of the first clock signal, and a second initial address of the second clock signal; and
the response from the digital fingerprint generation circuit to the challenge is the digital fingerprint, and the response is a physical unclonable function with respect to the first control word, the second control word, the first initial address of the first clock signal, and the second initial address of the second clock signal.

7. The digital fingerprint generation circuit according to claim 1 , wherein
the first clock generator is a clock generator based on a time-average-frequency direct period synthesis; and
the first clock generator is configured to periodically accumulate the first control words to generate first clock signals having different periods.

8. The digital fingerprint generation circuit according to claim 1 , wherein
the second clock generator is the clock generator based on a time-average-frequency direct period synthesis; and
the second clock generator is configured to periodically accumulate the second control words to generate second clock signals having different periods.

9. The digital fingerprint generation circuit according to claim 1 , wherein the fraction portion is 0.5.

10. The digital fingerprint generation circuit according to claim 1 , further comprising: a third clock generator and a fourth clock generator, wherein
the control unit is further electrically coupled with the third clock generator and the fourth clock generator, and the control unit is further configured to: generate a third control word and a fourth control word, transmit the third control word to the third clock generator, and transmit the fourth control word to the fourth clock generator;
the third clock generator is further electrically coupled with the frequency detector, and the third clock generator is configured to: generate a third clock signal based on the third control word and transmit the third clock signal to the frequency detector;
the fourth clock generator is further electrically coupled with the frequency detector, and the fourth clock generator is configured to: generate a fourth clock signal based on the fourth control word and transmit the fourth clock signal to the frequency detector; and
the frequency detector is further configured to generate the digital fingerprint of the integrated circuit based on any two of the first clock signal, the second clock signal, the third clock signal, and the fourth clock signal;
wherein the first clock generator, the second clock generator, the third clock generator, and the fourth clock generator have different manufacturing deviations from each other, and both of the third control word and the fourth control word have an integer portion and a fraction portion.

11. The digital fingerprint generation circuit according to claim 9 , further comprising: a clock source, wherein
the clock source is electrically coupled with the first clock generator, the second clock generator, the third clock generator, and the fourth clock generator, and configured to generate a clock signal.

12. The digital fingerprint generation circuit according to claim 11 , wherein the clock source is further electrically coupled with the control unit, and the control unit is further configured to configure a frequency of the clock signal generated by the clock source.

13. The digital fingerprint generation circuit according to claim 11 , wherein the frequency detector comprises a D flip-flop; the frequency detector is configured to: output a first parameter value in response to a difference between a period of the second clock signal and a period of the first clock signal being greater than or equal to a difference threshold; output a second parameter value in response to the difference between the period of the second clock signal and the period of the first clock signal being less than the difference threshold; wherein after a plurality of periods, the digital fingerprint of the integrated circuit is formed by at least one first parameter value and at least one second parameter value output by the frequency detector; the difference threshold is 0; the first parameter value is 1 and the second parameter value is 0;
an output of the frequency detector comprises a response to a challenge of the digital fingerprint generation circuit;
the challenge of the digital fingerprint generation circuit is a set comprising the first control word, the second control word, a first initial address of the first clock signal, and a second initial address of the second clock signal;
the response from the digital fingerprint generation circuit to the challenge is the digital fingerprint, and the response is a physical unclonable function with respect to the first control word, the second control word, the fi

Assignees

• Beijing Boe Technology Dev Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Wei Xiangye
• Bai Yiming
• Xiu Liming

Classifications

• G06F21/725 Primary

  operating on a secure reference time value · CPC title

• G06F1/08

  Clock generators with changeable or programmable clock frequency · CPC title

• G06F21/73 Primary

  by creating or determining hardware identification, e.g. serial numbers · CPC title

• G06F2221/2103

  Challenge-response · CPC title

• H04L9/3278 Primary

  using physically unclonable functions [PUF] · CPC title