Method for memory storage and access

Patent metadata

Field	Value
Publication number	US-11892906-B2
Application number	US-202117392415-A
Country	US
Kind code	B2
Filing date	Aug 3, 2021
Priority date	Aug 5, 2020
Publication date	Feb 6, 2024
Grant date	Feb 6, 2024

Abstract

A method for storing data bits in memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are stored in the memory cells. A method for reading data bits from memory cells, in which the data bits have at least one byte-filling bit, where at least one predefined functionality for a subset of the data bits is coded in the at least one byte-filling bit, and in which the data bits are read from the memory cells based on the coded predefined functionality. Corresponding apparatuses and memories are also disclosed.

First claim

What is claimed is:

1. A method for storing data bits having at least one byte-filling bit in memory cells, the method comprising:
coding, in the at least one-byte-filling bit, at least one predefined functionality for a subset of the data bits; and
storing the data bits in the memory cells,
wherein the data bits are grouped, together with check bits, into bytes, wherein at least one of these bytes can be corrected based on a byte error code, wherein the data bits and the check bits are stored in the memory cells,
wherein, in an error-free case, the data bits and the check bits represent a code word of the byte error code or are parts of a code word of the byte error code,
wherein the byte error code has N check bytes having check bits,
wherein a byte comprises m bits,
wherein there is a byte which has K byte-filling bits and m−K data bits,
wherein m is determined as a smallest positive integer so that
m ·(2 m− 1)≥ n +( N·m )+ K

where m≥3, 1≤K≤m−1, N≥2 and n>(N+2)·m, and
where n is a number of data bits.

2. The method of claim 1 , further comprising:
storing the data bits in the memory cells based on the at least one predefined functionality coded in the at least one byte-filling bit.

3. The method of the claim 1 , wherein the subset of the data bits comprises the data bits excluding the at least one byte-filling bit.

4. The method the of claim 1 , wherein the subset of the data bits comprises all of the data bits.

5. The method of claim 1 , wherein the at least one predefined functionality coded in the at least one byte-filling bit comprises one of:
a first value of the byte-filling bit indicates that the subset of the data bits is stored in an inverted manner and a second value of the byte-filling bit indicates that the subset of the data bits is stored in a non-inverted manner;
a first value of the byte-filling bit indicates that the subset of the data bits is invalid and a second value of the byte-filling bit indicates that the subset of the data bits is valid;
a first value of the byte-filling bit indicates that the subset of the data bits can be overwritten and a second value of the byte-filling bit indicates that the subset of the data bits cannot be overwritten;
a first value of the byte-filling bit indicates that the subset of the data bits cannot be read and a second value of the byte-filling bit indicates that the subset of the data bits can be read; or
a first value of the byte-filling bit indicates that the subset of the data bits is protected and a second value of the byte-filling bit indicates that the subset of the data bits is not protected.

6. The method of claim 1 , wherein the at least one byte-filling bit is used to detect errors in the data bits.

7. The method of claim 1 , wherein the check bits are determined based on address bits.

8. The method of claim 7 ,
wherein the byte error code has R address bytes determined from address bits,
wherein m is determined as a smallest positive integer so that
m ·(2 m −1)≥ n +( N·m )+( R·m )+ K

where m≥3, 1≤K≤m−1, N≥2, R≥1 and n>(N+R+2)·(m).

9. The method of claim 8 , wherein the address bits are part of the code word of the byte error code.

10. The method of claim 9 , wherein the address bits are not part of the code word of the byte error code.

11. A method for reading data bits having at least one byte-filling bit from memory cells, the method comprising:
coding, in the at least one byte-filling bit, at least one predefined functionality for a subset of the data bits; and
reading the data bits from the memory cells based on the at least one predefined functionality coded in the at least one byte-filling bit,
wherein the data bits are grouped, together with check bits, into bytes, wherein at least one of these bytes can be corrected based on a byte error code, wherein the data bits and the check bits are stored in the memory cells,
wherein, in an error-free case, the data bits and the check bits represent a code word of the byte error code or are parts of a code word of the byte error code, wherein the check bits are determined based on address bits,
wherein the byte error code has N check bytes,
wherein the byte error code has R address bytes determined from address bits,
wherein a byte comprises m bits,
wherein there is a byte which has K byte-filling bits and m−K data bits,
wherein m is determined as a smallest positive integer so that
m ·(2 m− 1)≥ n +( N·m )+( R·m )+ K

where m≥3, 1≤K≤m−1, N≥2, R≥1 and n>(N+R+2)·(m), and
where n is a number of data bits.

12. The method of claim 11 , further comprising:
determining, based on the data bits which have been read, whether there is a code word of the byte error code; and
detecting and/or correcting at least one error if there is no code word of the byte error code.

13. The method of claim 12 , wherein, if there is a code word of the byte error code and if at least one detected error has been corrected, the data bits which have been read are processed further.

14. A processor for storing and reading data bits having at least one byte-filling bit in memory cells of a memory, the processor configured to:
code, in the at least one-byte-filling bit, at least one predefined functionality for a subset of the data bits;
store the data bits in the memory cells; and
read the data bits from the memory cells based on the at least one predefined functionality coded in the at least one byte-filling bit,
wherein the data bits are grouped, together with check bits, into bytes, wherein at least one of these bytes can be corrected based on a byte error code, wherein the data bits and the check bits are stored in the memory cells,
wherein, in an error-free case, the data bits and the check bits represent a code word of the byte error code or are parts of a code word of the byte error code,
wherein the byte error code has N check bytes having check bits,
wherein a byte comprises m bits,
wherein there is a byte which has K byte-filling bits and m−K data bits,
wherein m is determined as a smallest positive integer so that
m ·(2 m− 1)≥ n +( N·m )+ K

where m≤3, 1≤K≤m−1, N≥2 and n>(N+2)·m, and
where n is a number of data bits.

15. The processor of claim 14 , wherein the processor is part of the memory or part of a memory management system.

16. The processor of claim 14 , wherein the memory comprises at least one of: a cache memory, a register or a register array, a flash memory, an MRAM, an SRAM, an RERAM, a PC-RAM, an FE-RAM, a CB-RAM, a multi-bit memory, a multi-level memory.

17. The processor of claim 14 , wherein the processor is further configured to:
determine, based on the data bits which have been read, whether there is a code word of the byte error code; and
detecting and/or correcting at least one error if there is no code word of the byte error code.

Assignees

• Infineon Technologies Ag

Inventors

• Kern Thomas
• Rabenalt Thomas
• Goessel Michael

Classifications

• G06F11/08 Primary

  Error detection or correction by redundancy in data representation, e.g. by using checking codes · CPC title

• G06F11/1012

  using codes or arrangements adapted for a specific type of error (G06F11/1048 takes precedence) · CPC title

• G11C29/18

  Address generation devices; Devices for accessing memories, e.g. details of addressing circuits · CPC title

• G11C29/42 Primary

  using error correcting codes [ECC] or parity check · CPC title

• G11C29/4401

  for self repair · CPC title