Isolation circuit system and signal isolation method thereof

Patent metadata

Field	Value
Publication number	US-11888307-B2
Application number	US-201917288495-A
Country	US
Kind code	B2
Filing date	Oct 10, 2019
Priority date	Dec 3, 2018
Publication date	Jan 30, 2024
Grant date	Jan 30, 2024

Abstract

Isolation circuit system and a signal isolation method thereof. The system includes: a power management unit, configured to output a first signal to a digital logic circuit when power down is detected in a first circuit area, and output a second signal to the digital logic circuit when no power down is detected in the first circuit area; the digital logic circuit, configured to perform logical processing on the first signal received from the power management unit before outputting an isolation signal to the isolation circuit, and perform logical processing on the second signal received from the power management unit before outputting a connection signal to the isolation circuit; and the isolation circuit, configured to block the interactive signal, or to output the interactive signal to a second circuit area after the interactive signal is processed through voltage stabilization.

First claim

What is claimed is:

1. An isolation circuit system, comprising a power management unit, a digital logic circuit and an isolation circuit, wherein
the power management unit is configured to output a first signal to a digital logic circuit when power down is detected in a first circuit area, and output a second signal to the digital logic circuit when no power down is detected in the first circuit area;
the digital logic circuit is configured to perform logical processing on the first signal received from the power management unit before outputting an isolation signal to the isolation circuit, and perform logical processing on the second signal received from the power management unit before outputting a connection signal to the isolation circuit; and
the isolation circuit is configured to simultaneously receive an interactive signal from the first circuit area and the isolation signal from the digital logic circuit and block the interactive signal, or to simultaneously receive the interactive signal from the first circuit area and the connection signal from the digital logic circuit and output the interactive signal to a second circuit area after the interactive signal is processed through voltage stabilization,
wherein the interactive signal outputted from the first circuit area comprises a write enable signal and a data signal, and
wherein the second circuit area comprises a register, and the isolation circuit is configured to output the interactive signal to the register of the second circuit area after the interactive signal is processed through the voltage stabilization when simultaneously receiving the interactive signal from the first circuit area and the connection signal from the digital logic circuit.

2. The system according to claim 1 , further comprising:
a microprocessor, configured to output a third signal to the digital logic circuit when the power down is detected in the first circuit area, and output a fourth signal to the digital logic circuit when no power down is detected in the first circuit area;
the digital logic circuit, configured to perform logical processing on the first signal received from the power management unit and the third signal received from the microprocessor before outputting the isolation signal to the isolation circuit, and perform logical processing on the second signal received from the power management unit and the fourth signal received from the microprocessor before outputting the connection signal to the isolation circuit.

3. The system according to claim 2 , wherein the digital logic circuit comprises a NOR gate, and two input ends of the NOR gate are respectively connected to output ends of the power management unit and the microprocessor, and an output end of the NOR gate is connected to the isolation circuit.

4. The system according to claim 1 , wherein the digital logic circuit is configured to perform a NOT processing on the first signal or the second signal to generate the corresponding isolation signal or connection signal.

5. The system according to claim 1 , wherein the isolation circuit comprises at least one AND gate, two input ends of each AND gate are respectively connected to the output end of the digital logic circuit and one output end of the first circuit area.

6. The system according to claim 5 , wherein the interactive signal comprises a data signal, and the system further comprises:
a buffer module, connected between the output end of the digital logic circuit and an input end of the AND gate to which the data signal is inputted, and configured to buffer the isolation signal/connection signal outputted by the digital logic circuit and then output the isolation signal/connection signal to the second circuit area after the isolation signal/connection signal is processed through the voltage stabilization.

7. The system according to claim 1 , wherein the first circuit area is a power down area, the second circuit area is a normally open voltage domain.

8. A signal isolation method, comprising:
outputting, by a power management unit, a first signal to a digital logic circuit when power down is detected in a first circuit area, and outputting a second signal to the digital logic circuit when no power down is detected in the first circuit area;
performing, by the digital logic circuit, logical processing on the first signal received from the power management unit before outputting an isolation signal to an isolation circuit, and performing logical processing on the second signal received from the power management unit before outputting a connection signal to the isolation circuit; and
simultaneously receiving, by the isolation circuit, an interactive signal from the first circuit area and the isolation signal from the digital logic circuit, and blocking the interactive signal, or simultaneously receiving the interactive signal from the first circuit area and the connection signal from the digital logic circuit, and outputting the interactive signal to a second circuit area after the interactive signal is processed through voltage stabilization,
wherein the interactive signal comprises a data signal, and the receiving, by the isolation circuit, the isolation signal/connection signal from the digital logic circuit comprises receiving, by the isolation circuit, the isolation signal/connection signal from the digital logic circuit through a buffer module.

9. The method according to claim 8 , further comprising:
outputting, by a microprocessor, a third signal to the digital logic circuit when the power down is detected in the first circuit area, and outputting a fourth signal to the digital logic circuit when no power down is detected in the first circuit area;
wherein the performing, by the digital logic circuit, logical processing on the first signal received from the power management unit before outputting the isolation signal to the isolation circuit, and performing logical processing on the second signal received from the power management unit before outputting the connection signal to the isolation circuit comprises:
performing logical processing on the first signal received from the power management unit and the third signal received from the microprocessor before outputting the isolation signal to the isolation circuit, and performing logical processing on the second signal received from the power management unit and the fourth signal received from the microprocessor before outputting the connection signal to the isolation circuit.

Assignees

• Gree Electric Appliances Inc Zhuhai

Inventors

• Huang Qiao

Classifications

• H02H3/12 Primary

  responsive to underload or no-load {(for motors H02H7/0827)} · CPC title

• G06F1/28 Primary

  Supervision thereof, e.g. detecting power-supply failure by out of limits supervision · CPC title

• G06F1/305

  in the event of power-supply fluctuations · CPC title

• H02H1/0007

  concerning the detecting means (in general G01R or other subclasses of G01; reed switches H01H71/2445) · CPC title

• G06F2119/06

  Power analysis or power optimisation · CPC title