Pixel circuit and driving method thereof, and display panel

Patent metadata

Field	Value
Publication number	US-11887540-B2
Application number	US-202217990070-A
Country	US
Kind code	B2
Filing date	Nov 18, 2022
Priority date	Nov 26, 2020
Publication date	Jan 30, 2024
Grant date	Jan 30, 2024

Abstract

A pixel circuit, a driving method thereof, and a display panel. The pixel circuit includes a drive module, a first initialization module and a data write module. The drive module is configured to generate, in response to a data signal, a drive current to drive a light-emitting element to emit light. The first initialization module is controlled by a first scan signal and a second scan signal and is configured to initialize a control terminal of the drive module when the first scan signal and the second scan signal are active. The data write module is controlled by a third scan signal, where the first initialization module is configured to cooperate with the data write module to write the data signal into the control terminal of the drive module when the second scan signal and the third scan signal are active.

First claim

What is claimed is:

1. A pixel circuit, comprising:
a drive module further comprising a drive transistor, configured to generate, in response to a data signal, a drive current to drive a light-emitting element to emit light;
a first initialization module further comprising a first transistor and a second transistor, controlled by a first scan signal and a second scan signal and is configured to initialize a control terminal of the drive module when the first scan signal and the second scan signal are active; and
a data write module further comprising a third transistor, controlled by a third scan signal, wherein the first initialization module is configured to cooperate with the data write module to write the data signal into the control terminal of the drive module when the second scan signal and the third scan signal are active;
wherein the first scan signal, the second scan signal and the third scan signal have a same waveform shape and a same delay time interval, and scan signals of the pixel circuit multiplex scan signals of previous pixel circuits.

2. The pixel circuit of claim 1 , wherein
a gate of the first transistor is configured to receive the first scan signal, and a first electrode of the first transistor is configured to receive a first initialization signal; and
wherein a gate of the second transistor is configured to receive the second scan signal, a first electrode of the second transistor is electrically connected to a second electrode of the first transistor, and a second electrode of the second transistor is electrically connected to the control terminal of the drive module.

3. The pixel circuit of claim 2 , wherein the first transistor is a low-temperature polysilicon transistor or an oxide transistor, and the second transistor is an oxide transistor.

4. The pixel circuit of claim 2 , wherein the first electrode of the second transistor is further electrically connected to a first terminal of the drive module; and wherein a gate of the third transistor is configured to receive the third scan signal, a first electrode of the third transistor is configured to receive the data signal, and a second electrode of the third transistor is electrically connected to a second terminal of the drive module.

5. The pixel circuit of claim 1 , further comprising:
a first light emission control module further comprising a fourth transistor, wherein a control terminal of the first light emission control module is configured to receive a light emission control signal, a first terminal of the first light emission control module is configured to receive a first power supply signal, and a second terminal of the first light emission control module is electrically connected to a first terminal of the drive module; and
a second light emission control module further comprising a fifth transistor, wherein a control terminal of the second light emission control module is configured to receive the light emission control signal, a first terminal of the second light emission control module is electrically connected to a second terminal of the drive module, and a second terminal of the second light emission control module is electrically connected to the light-emitting element.

6. The pixel circuit of claim 5 , wherein the drive transistor is an N-type transistor, and the first power supply signal is multiplexed as a first initialization signal.

7. The pixel circuit of claim 6 , wherein a gate of the drive transistor is used as the control terminal of the drive module, a source of the drive transistor is used as the second terminal of the drive module, and a drain of the drive transistor is used as the first terminal of the drive module.

8. The pixel circuit of claim 6 , wherein a gate of the fourth transistor is configured to receive the light emission control signal, a first electrode of the fourth transistor is configured to receive the first power supply signal, and a second electrode of the fourth transistor is electrically connected to a drain of the drive transistor; and
wherein a gate of the fifth transistor is configured to receive the light emission control signal, a first electrode of the fifth transistor is electrically connected to a source of the drive transistor, and a second electrode of the fifth transistor is electrically connected to the light-emitting element.

9. The pixel circuit of claim 5 , wherein the first power supply signal is a direct current power supply signal.

10. The pixel circuit of claim 5 , wherein an effective-level stage of the first scan signal overlaps with an effective-level stage of the second scan signal;
the effective-level stage of the second scan signal overlaps with an effective-level stage of the third scan signal; and
an effective-level stage of the light emission control signal does not overlap with the effective-level stage of the first scan signal, the effective-level stage of the second scan signal, and the effective-level stage of the third scan signal.

11. The pixel circuit of claim 1 , further comprising:
a storage module, wherein a first terminal of the storage module is electrically connected to the control terminal of the drive module, and a second terminal of the storage module is electrically connected to the light-emitting element; and
a second initialization module further comprising at least a sixth transistor, wherein a control terminal of the second initialization module is configured to receive the first scan signal, a first terminal of the second initialization module is configured to receive a second initialization signal, and a second terminal of the second initialization module is electrically connected to the light-emitting element.

12. The pixel circuit of claim 11 , wherein the storage module is configured to store a potential of the control terminal of the drive module, to enable the drive module to generate a stable drive current in a light emission stage.

13. The pixel circuit of claim 11 , wherein the second initialization signal is a direct current reset signal.

14. The pixel circuit of claim 11 , a gate of the sixth transistor is configured to receive the first scan signal, a first electrode of the sixth transistor is configured to receive the second initialization signal, and a second electrode of the sixth transistor is electrically connected to an anode of the light-emitting element; and
wherein the storage module comprises a capacitor, a first terminal of the capacitor is electrically connected to a gate of the drive transistor, and a second terminal of the capacitor is electrically connected to the second electrode of the sixth transistor.

15. The pixel circuit of claim 1 , wherein the drive module comprises the control terminal, a first terminal and a second terminal, and the first initialization module comprises a first control terminal, a second control terminal, an initialization signal input terminal, a data signal input terminal, and an output terminal, wherein the first control terminal of the first initialization module is configured to receive the first scan signal, the second control terminal of the first initialization module is configured to receive the second scan signal, the initialization signal input terminal is configured to receive a first initialization signal, the data signal input terminal is electrically connected to the first terminal of the drive module, and the output terminal of the first initialization module is electrically connected to the control terminal of the drive module; and
wherein the data write module comprises a control terminal, an input terminal and an output terminal, wherein the control terminal

Assignees

• Hefei Visionox Tech Co Ltd

Inventors

• Mi Lei

Classifications

• G09G3/3233 Primary

  with pixel circuitry controlling the current through the light-emitting element · CPC title

• G09G3/3266

  Details of drivers for scan electrodes · CPC title

• G09G3/3275

  Details of drivers for data electrodes · CPC title

• G09G2300/0819

  used for counteracting undesired variations, e.g. feedback or autozeroing · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title