Semiconductor memory device with high electron mobility channels and method of manufacturing the same

Patent metadata

Field	Value
Publication number	US-11882703-B2
Application number	US-202117377117-A
Country	US
Kind code	B2
Filing date	Jul 15, 2021
Priority date	Jan 7, 2021
Publication date	Jan 23, 2024
Grant date	Jan 23, 2024

Abstract

Provided herein may be a semiconductor memory device and a method of manufacturing the semiconductor memory device. The semiconductor memory device may include a stacked body including a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate, and a plurality of channel structures configured to vertically pass through the stacked body. Each of the plurality of channel structures may include a core insulating layer, a first channel layer, a second channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate. Electron mobility of the first channel layer may be higher than electron mobility of the second channel layer.

First claim

What is claimed is:

1. A semiconductor memory device, comprising:
a stacked body comprising a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate; and
a plurality of channel structures configured to vertically pass through the stacked body,
wherein each of the plurality of channel structures comprises a core insulating layer, a first channel layer, a second channel layer, a third channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate,
wherein the first channel layer encloses a surface of the core insulating layer, the second channel layer encloses a surface of the first channel layer, and the third channel layer encloses a surface of the second channel layer,
wherein the first channel layer and the third channel layer are formed of a same material, and
wherein electron mobility of each of the first channel layer and the third channel layer is higher than electron mobility of the second channel layer.

2. The semiconductor memory device according to claim 1 , wherein the first channel layer and the third channel layer are silicon germanium layers, and the second channel layer is a polysilicon layer.

3. The semiconductor memory device according to claim 1 , wherein the first channel layer and the third channel layer prevent oxygen from being diffused and introduced from the tunnel insulating layer and the core insulating layer.

4. The semiconductor memory device according to claim 1 , wherein the electron mobility of the second channel layer increases due to tensile stress caused by the first channel layer and the third channel layer.

5. A semiconductor memory device, comprising:
a stacked body comprising a plurality of interlayer insulating layers and a plurality of gate electrodes that are alternately stacked on a substrate; and
a plurality of channel structures configured to vertically pass through the stacked body,
wherein each of the plurality of channel structures comprises a core insulating layer, a first channel layer, a second channel layer, a third channel layer, a tunnel insulating layer, and a charge storage layer that extend vertically towards the substrate,
wherein the first channel layer encloses the core insulating layer, the second channel layer encloses the first channel layer, and the third channel layer encloses the second channel layer,
wherein the first channel layer and the third channel layer are formed of a same material, and
wherein electron mobility of the second channel layer is higher than electron mobility of each of the first channel layer and the third channel layer.

6. The semiconductor memory device according to claim 5 , wherein the first channel layer and the third channel layer are polysilicon layers, and the second channel layer is a silicon germanium layer.

7. The semiconductor memory device according to claim 5 , wherein the electron mobility of the first channel layer increases due to tensile stress caused by the second channel layer and the third channel layer.

8. A method of manufacturing a semiconductor memory device, comprising:
forming a stacked body by alternately stacking a plurality of interlayer insulating layers and a plurality of sacrificial layers on a substrate;
forming a plurality of holes configured to vertically pass through the stacked body; and
successively forming a blocking insulating layer, a charge storage layer, a tunnel insulating layer, a first channel layer, a second channel layer, and a third channel layer on a sidewall of each of the plurality of holes,
wherein the first channel layer and the third channel layer are formed of a same material, and
wherein the second channel layer is a material layer having higher electron mobility than each of the first channel layer and the third channel layer.

9. The method according to claim 8 , wherein the first channel layer and the third channel layer are formed of a polysilicon layer, and the second channel layer is formed of a silicon germanium layer.

10. The method according to claim 9 , wherein the first channel layer, the second channel layer, and the third channel layer are formed by using an ALD process and formed by using a super cycle method in which numbers of Si cycles and Ge cycles are controlled.

11. A method of manufacturing a semiconductor memory device, comprising:
forming a stacked body by alternately stacking a plurality of interlayer insulating layers and a plurality of sacrificial layers on a substrate;
forming a plurality of holes configured to vertically pass through the stacked body; and
successively forming a blocking insulating layer, a charge storage layer, a tunnel insulating layer, a first channel layer, a second channel layer, and a third channel layer on a sidewall of each of the plurality of holes,
wherein the first channel layer and the third channel layer are formed of a same material, and
wherein each of the first channel layer and the third channel layer is a material layer having higher electron mobility than the second channel layer.

12. The method according to claim 11 , wherein the first channel layer and the third channel layer are formed of a silicon germanium layer, and the second channel layer is formed of a polysilicon layer.

Assignees

• Sk Hynix Inc

Inventors

• Lim Sungmook
• Yun dae hwan
• Choi Gil Bok
• Shin Jae Hyeon
• Yang In Gon
• Choi Hyung Jin

Classifications

• H10P14/3456

  Polycrystalline · CPC title

• H10P14/3411

  Silicon, silicon germanium or germanium · CPC title

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10D62/822

  comprising only Group IV materials heterojunctions, e.g. Si/Ge heterojunctions · CPC title

• H10D62/40

  Crystalline structures · CPC title