Techniques to reduce the effect of pad asymmetry and signal routing on resolution of PWM or PFM signals

Patent metadata

Field	Value
Publication number	US-11881861-B2
Application number	US-202217584836-A
Country	US
Kind code	B2
Filing date	Jan 26, 2022
Priority date	Jan 26, 2022
Publication date	Jan 23, 2024
Grant date	Jan 23, 2024

Abstract

Some examples relate to a system including a pulse modulation (PM) circuit having a PM input and a PM output. The system also includes a load circuit having a load circuit input, and an I/O pad coupling the PM output to the load circuit input. An asymmetry detection circuit has a first asymmetry detection (AD) input coupled to the PM output via a first feedback path, a second AD input coupled to an output node of the I/O pad via a second feedback path, and an AD output coupled to the PM input of the pulse modulation circuit via a control path.

First claim

What is claimed is:

1. A system comprising:
a pulse modulation circuit having a pulse modulation (PM) input and a PM output;
a load circuit having a load circuit input;
an I/O pad coupling the PM output to the load circuit input; and
an asymmetry detection circuit having a first asymmetry detection (AD) input coupled to the PM output via a first feedback path, a second AD input coupled to an output node of the I/O pad via a second feedback path, and an AD output coupled to the PM input via a control path.

2. The system of claim 1 , wherein the pulse modulation circuit is configured to provide a pulse width modulated (PWM) or pulse frequency modulated (PFM) signal to the load circuit input via the I/O pad, and the I/O pad is configured to provide a modified PWM or PFM signal to the load circuit input based on the PWM or PFM signal.

3. The system of claim 2 , wherein the asymmetry detection circuit is configured to provide a control signal to the PM input via the control path, the control signal being indicative of an asymmetry between a rising edge duration of the modified PWM or PFM signal and a falling edge duration of the modified PWM or PFM signal during a first time interval, and being used to tune the PWM or PFM signal for a second time interval after the first time interval to limit the asymmetry.

4. The system of claim 2 , wherein the asymmetry detection circuit is configured to provide a control signal to the PM input via the control path, the control signal being indicative of an asymmetry between the PWM or PFM signal and the modified PWM or PFM signal for a first time interval and being used to tune the PWM or PFM signal for a second time interval after the first time interval to limit the asymmetry.

5. The system of claim 4 , wherein during the first time interval, the modified PWM or PFM signal has a rising edge that has a rising edge time difference relative to a corresponding rising edge of the PWM or PFM signal and has a falling edge that has a falling edge time difference relative to a corresponding falling edge of the PWM or PFM signal.

6. The system of claim 5 , wherein the asymmetry detection circuit is configured to provide the control signal to the PM input to adjust the PWM or PFM signal so the rising edge time difference is equal to the falling edge time difference for the second time interval.

7. The system of claim 2 , wherein the asymmetry detection circuit is configured to provide a control signal to the pulse modulation circuit to adjust the PWM or PFM signal, wherein the control signal is indicative of an asymmetry between: (1) a rising edge time difference between a rising edge of the PWM or PFM signal and a corresponding rising edge of the modified PWM or PFM signal and (2) a falling edge time difference between a falling edge of the PWM or PFM signal and a corresponding falling edge of the modified PWM or PFM signal.

8. The system of claim 7 , wherein the asymmetry detection circuit is configured to generate a first signal representing the rising edge time difference and a second signal representing the falling edge time difference, to subtract the second signal from the first signal and pass the resulting subtracted signal through a low pass filter to the AD output.

9. The system of claim 7 , wherein the load circuit is a DC-to-DC converter, the system further comprising:
a DC-to-DC feedback path coupling an output of the DC-to-DC converter to the pulse modulation circuit, wherein the pulse modulation circuit adjusts the PWM or PFM signal based on both the asymmetry between the rising edge time difference and the falling edge time difference and an error signal provided by the DC-to-DC feedback path.

10. The system of claim 7 , wherein the I/O pad comprises a metal pad, and an n-type transistor and a p-type transistor coupled to the metal pad, wherein the PM output is coupled to the n-type transistor and the p-type transistor which are in turn coupled to the metal pad to define the output node of the I/O pad, the output node being coupled to the load circuit input.

11. An integrated circuit comprising:
a pulse modulation circuit having a pulse modulation (PM) output that is configured to provide a pulse width modulated (PWM) or pulse frequency modulated (PFM) signal;
an I/O pad including an I/O pad input and an I/O pad output, the I/O pad input coupled to the PM output and the I/O pad output configured to provide a modified PWM or PFM signal to a load circuit, the modified PWM or PFM signal based on the PWM or PFM signal; and
an asymmetry detection circuit having a first asymmetry detection (AD) input coupled to the PM output via a first feedback path, a second AD input coupled to I/O pad output via a second feedback path, and an AD output coupled to the pulse modulation circuit via a control path on which a control signal is provided to the pulse modulation circuit, the control signal being based on a difference between the first AD input and the second AD input and being operative to adjust the modified PWM or PFM signal.

12. The integrated circuit of claim 11 , wherein the I/O pad comprises an n-type transistor and a p-type transistor coupled to a metal pad, the integrated circuit further comprising:
a bias adjust circuit having an input coupled to the AD output, the bias adjust circuit configured to adjust a current or voltage provided to the n-type transistor or the p-type transistor based on the control signal.

13. The integrated circuit of claim 11 , wherein the pulse modulation circuit is configured to adjust a duty cycle or a rising edge or a falling edge of the PWM or PFM signal based on the control signal.

14. The integrated circuit of claim 13 , wherein the asymmetry detection circuit is configured to determine an asymmetry between a first time corresponding to a rising edge of the PWM or PFM signal and a corresponding rising edge of a clock signal and a second time corresponding to a falling edge of the PWM or PFM signal and a corresponding falling edge of the clock signal, and to provide the control signal to adjust the PWM or PFM signal based on the asymmetry.

15. The integrated circuit of claim 11 , wherein the load circuit is a DC-to-DC converter.

16. A method, comprising:
providing a PWM or PFM signal to an input of an I/O pad;
providing a modified PWM or PFM signal from an output of the I/O pad, the modified PWM or PFM signal based on the PWM or PFM signal; and
determining a control signal based on a difference between the PWM or PFM signal for one or more first clock cycles and the modified PWM or PFM signal for the one or more first clock cycles; and
adjusting the PWM or PFM signal for consecutive clock cycles after the one or more first clock cycles, wherein the adjusting is based on the control signal.

17. The method of claim 16 , wherein the modified PWM or PFM signal is based on the PWM or PFM signal but has a rising edge or falling edge that has a time difference relative to a corresponding rising or falling edge of the PWM or PFM signal.

18. The method of claim 16 , wherein the modified PWM or PFM signal is based on the PWM or PFM signal but has a rising edge that has a rising edge time difference relative to a corresponding rising edge of the PWM or PFM signal and has a falling edge that has a falling edge time difference relative to a corresponding falling edge of the PWM or PFM signal.

19. The method of claim 18 , wherein the rising edge time difference differs from the falling edge time difference due to an asymmetry between a fall time of an n-type transistor of the I/O

Assignees

• Infineon Technologies Ag

Inventors

• Manjunath Sunanda
• Dewan Ketan
• Schaefer Juergen

Classifications

• H03K5/1534 Primary

  Transition or edge detectors · CPC title

• H03K5/05

  by the use of clock signals or other time reference signals · CPC title

• H03K5/086 Primary

  generated by feedback · CPC title

• H03K7/08

  Duration or width modulation {; Duty cycle modulation} · CPC title

• H03K19/17744

  for input/output signals · CPC title