Primitive fragment processing in the rasterization phase of a graphics processing system

Patent metadata

Field	Value
Publication number	US-11880933-B2
Application number	US-202117331537-A
Country	US
Kind code	B2
Filing date	May 26, 2021
Priority date	Jun 19, 2019
Publication date	Jan 23, 2024
Grant date	Jan 23, 2024

Abstract

Systems and methods for processing primitive fragments in a rasterization phase of a graphics processing system wherein a rendering space is subdivided into a plurality of tiles. The method includes receiving a plurality of primitive fragments, each primitive fragment corresponding to a pixel sample in a tile; determining whether a depth buffer read is to be performed for hidden surface removal processing of one or more of the primitive fragments; sorting the primitive fragments into a priority queue and a non-priority queue based on the depth buffer read determinations; and performing hidden surface removal processing on the primitive fragments in the priority and non-priority queues wherein priority is given to the primitive fragments in the priority queue.

First claim

What is claimed is:

1. Hidden surface removal logic circuitry for use in a graphics processing system in which a rendering space is subdivided into a plurality of tiles and each tile comprises a plurality of pixel samples, the hidden surface removal logic circuitry configured to:
receive a primitive fragment of a set of primitive fragments associated with a tile of the plurality of tiles, the primitive fragment corresponding to a pixel sample of the tile;
receive information indicating whether the primitive fragment requires a depth buffer read for full resolution depth testing;
if the primitive fragment is a first primitive fragment in the set, initialize a current best depth value buffer for the tile and a depth value update map for the tile, wherein the current best depth value buffer for the tile comprises a depth value for each pixel sample of the tile, the depth value update map indicates which values of the current best depth value buffer have been updated, and the depth value update map is initialized to indicate that no depth values in the current best depth value buffer have been updated;
determine whether the primitive fragment has a best depth value for the pixel sample corresponding to the primitive fragment according to a depth compare mode; and
in response to determining that the primitive fragment has the best depth value for the pixel sample corresponding to the primitive fragment, update the depth value for that pixel sample in the current best depth value buffer with the depth of the primitive fragment, and update the depth value update map to indicate that the depth value for that pixel sample has been updated;
wherein, when the first primitive fragment does not require a depth buffer read, initializing the current best depth value buffer comprises initializing each depth value in the current best depth value buffer to a worst depth value according to the depth compare mode, and, when the first primitive fragment requires a depth buffer read, initializing the current best depth value buffer comprises initializing each depth value in the current best depth value buffer to the corresponding depth value in the depth buffer for the tile.

2. The hidden surface removal logic circuitry of claim 1 , wherein the hidden surface removal logic circuitry is further configured to, if the primitive fragment is not the first primitive fragment in the set, but is a first in the set to require a depth buffer read for full resolution depth testing, update all depth values in the current best depth value buffer, except those depth values identified in the depth value update map as having been updated, with a corresponding depth value in a depth buffer for the tile stored in memory.

3. The hidden surface removal logic circuitry of claim 1 , wherein the hidden surface removal logic circuitry is configured to determine whether the primitive fragment has the best depth value for the pixel sample corresponding to the primitive fragment by comparing a depth of the primitive fragment to the depth value for that pixel sample in the current best depth value buffer.

4. The hidden surface removal logic circuitry of claim 3 , wherein the hidden surface removal logic circuitry is configured to determine that the primitive fragment has the best depth value for the pixel sample corresponding to the primitive fragment if it is determined from the comparison that the primitive fragment has a better depth than the depth value for that pixel sample in the current best depth value buffer according to the depth compare mode.

5. The hidden surface removal logic circuitry of claim 4 , wherein the depth compare mode is the less than depth compare mode, and the hidden surface removal logic circuitry is configured to determine that the primitive fragment has a better depth than the depth value for that pixel sample in the current best depth value buffer if it is determined from the comparison that the depth of the primitive fragment is less than the depth value for that pixel sample in the current best depth value buffer.

6. The hidden surface removal logic circuitry of claim 1 , wherein the hidden surface removal logic circuitry is configured to:
receive information indicating whether full resolution depth testing needs to be performed for the primitive fragment; and
determine whether the primitive fragment has the best depth value for the pixel sample corresponding to the primitive fragment by:
if full resolution depth testing does not need to be performed for the primitive fragment, determining that the primitive fragment has the best depth value for the pixel sample corresponding to the primitive fragment, and
if full resolution depth testing does need to be performed for the primitive fragment, comparing the depth of the primitive fragment to the depth value for that pixel sample in the current best depth value buffer.

7. The hidden surface removal logic circuitry of claim 1 , wherein the hidden surface removal logic circuitry is further configured to, in response to determining that the primitive fragment does not have the best depth value for the corresponding pixel sample, discard the primitive fragment.

8. The hidden surface removal logic circuitry of claim 1 , wherein the hidden surface removal logic circuitry is further configured to, in response to determining that the primitive fragment has the best depth value for the corresponding pixel sample, send the primitive fragment for further processing.

9. The hidden surface removal logic circuitry of claim 8 , wherein sending the primitive fragment for further processing comprises sending an identifier of the primitive fragment to a tag buffer.

10. The hidden surface removal logic circuitry of claim 1 , wherein the hidden surface removal logic circuitry is further configured to, if the primitive fragment is a last primitive fragment in the set of primitive fragments, write, to the depth buffer in memory, each depth value in the current best depth value buffer that the depth value update map indicates has been updated.

11. A graphics processing system comprising the hidden surface removal logic circuitry as set forth in claim 1 .

12. The graphics processing system of claim 11 , further comprising coarse depth test logic circuitry comprising:
hidden depth test logic circuitry configured to:
receive a set of one or more primitives related to one of the plurality of tiles;
obtain a depth range for the tile, the depth range for the tile identifying a depth range based on primitives previously processed for the tile; and
for at least one primitive in the set of one or more primitives:
make a determination, based on the depth range for the tile, as to whether all or a portion of the primitive is hidden in the tile, wherein if a determination is made that at least a portion of the primitive is hidden in the tile, full resolution depth testing is not performed on that portion of the primitive in respect of the tile; and
in response to making a determination that at least a portion of the primitive is not hidden in the tile, outputting at least that portion of the primitive; and

front depth test logic circuitry configured to receive the primitives output by the hidden depth test logic circuitry, or one or more primitive fragments generated therefrom, and for at least one of the received primitives or at least one of the primitive fragments:
make a determination, based on the depth range for the tile, as to whether the primitive or primitive fragment has better depth than the primitives previously processed for the tile according to the depth compare mode; and
in response to making a determination that the primitive or primitive fragment has bett

Assignees

• Imagination Tech Ltd

Inventors

• Brigg Robert
• Belli Lorenzo

Classifications

• G06T15/405 Primary

  using Z-buffer · CPC title

• G06F7/24

  Sorting, i.e. extracting data from one or more carriers, rearranging the data in numerical or other ordered sequence, and rerecording the sorted data on the original carrier or on a different carrier or set of carriers {sorting methods in general}(G06F7/36 takes precedence) · CPC title

• G06F9/4881

  Scheduling strategies for dispatcher, e.g. round robin, multi-level priority queues · CPC title

• G06T1/60

  Memory management · CPC title

• G06T7/50

  Depth or shape recovery · CPC title