Semiconductor memory and method for writing data

Patent metadata

Field	Value
Publication number	US-11880585-B2
Application number	US-202117510386-A
Country	US
Kind code	B2
Filing date	Oct 26, 2021
Priority date	Apr 1, 2021
Publication date	Jan 23, 2024
Grant date	Jan 23, 2024

Abstract

Embodiments relate to a semiconductor memory and a method for writing data. The semiconductor memory includes: at least one storage array, the storage array including a plurality of data storage units and a plurality of check bit storage units; a check module, configured to receive written data and generate check data according to the written data; and a data transmission module, respectively connected to the check module and the storage array, the data transmission module being configured to transmit the written data to the plurality of data storage units and transmit the check data to the plurality of check bit storage units. A first transmission time duration of the check data is shorter than a second transmission time duration of the written data.

First claim

What is claimed is:

1. A semiconductor memory, comprising:
at least one storage array, the storage array comprising a plurality of data storage units and a plurality of check bit storage units;
a check module, configured to receive written data and generate check data according to the written data; and
a data transmission module, respectively connected to the check module and the at least one storage array, the data transmission module being configured to transmit the written data to the plurality of data storage units and transmit the check data to the plurality of check bit storage units;
wherein a first transmission time duration of the check data is shorter than a second transmission time duration of the written data, the first transmission time duration being a time duration required for transmitting the check data from the data transmission module to the plurality of check bit storage units, and the second transmission time duration being a time duration required for transmitting the written data from the data transmission module to the plurality of data storage units;
wherein the check module comprises a first check unit and a second check unit, the data transmission module comprising a first transmission unit and a second transmission unit, one of two of the plurality of storage units positioned in adjacent columns being connected to the first check unit via the first transmission unit, and the other one of two of the plurality of storage units being connected to the second check unit via the second transmission unit.

2. The semiconductor memory according to claim 1 , wherein a first transmission path of the check data is shorter than a second transmission path of the written data, the first transmission path being a path between the data transmission module and each of the plurality of check bit storage units, and the second transmission path being a path between the data transmission module and each of the plurality of data storage units; and
wherein the first transmission path corresponds to the first transmission time duration, and the second transmission path corresponds to the second transmission time duration.

3. The semiconductor memory according to claim 2 , wherein the check data comprises error correction check data, the written data and the error correction check data both comprising a plurality of data bits, and number of data bits of the written data being more than number of data bits of the error correction check data, the check module comprising:
an error correction check unit, connected to the data transmission module, the error correction check unit being configured to generate the error correction check data according to the written data;
wherein data of one of the plurality of data bits are correspondingly stored in one of the plurality of data storage units or one of the plurality of check bit storage units, a transmission time duration required for the written data, configured for defining each of the plurality of data bits, to be transmitted from the data transmission module to a corresponding one of the plurality of data storage units being a data transmission time duration, and a transmission time duration required for the error correction check data, configured for defining each of the plurality of data bits, to be transmitted from the data transmission module to a corresponding one of the plurality of check bit storage units being a check transmission time duration.

4. The semiconductor memory according to claim 3 , wherein the first transmission time duration is a maximum value among a plurality of check transmission time durations, the second transmission time duration being a minimum value of a plurality of data transmission time durations.

5. The semiconductor memory according to claim 3 , wherein the first transmission time duration is an average value among a plurality of check transmission time durations, the second transmission time duration being an average value of a plurality of data transmission time durations.

6. The semiconductor memory according to claim 3 , wherein the first transmission time duration is a maximum value among a plurality of check transmission time durations, the second transmission time duration being a maximum value among a plurality of data transmission time durations.

7. The semiconductor memory according to claim 2 , wherein the check data comprise parity check data, the written data comprising a plurality of data bits, the parity check data comprising one data bit, and the check module comprising:
a parity check unit, connected to the data transmission module, the parity check unit being configured to generate the parity check data according to the written data;
wherein data of one of the plurality of data bits are correspondingly stored in one of the plurality of data storage units or one of the plurality of check bit storage units, a transmission time duration required for the written data, configured for defining each of the plurality of data bits, to be transmitted from the data transmission module to a corresponding one of the plurality of data storage units being a data transmission time duration, and a transmission time duration required for the parity check data, configured for defining each of the plurality of data bits, to be transmitted from the data transmission module to a corresponding one of the plurality of check bit storage units being a check transmission time duration.

8. The semiconductor memory according to claim 7 , wherein the first transmission time duration is the check transmission time duration, the second transmission time duration being a minimum value among a plurality of data transmission time durations.

9. The semiconductor memory according to claim 2 , wherein a differential between the first transmission time duration and the second transmission time duration is greater than a preset time duration, the preset time duration being a time duration required for generating the check data by the check module based on the written data.

10. The semiconductor memory according to claim 9 , wherein the preset time duration ranges from 0.5 ns to 1 ns.

11. The semiconductor memory according to claim 1 , further comprising:
a plurality of bit line pairs, each of the plurality of bit line pairs comprising a first bit line and a second bit line, the first bit line and the second bit line being configured to transmit opposite signals, and the plurality of storage units positioned in the same column being connected to the same one of the plurality of bit line pairs;
a plurality of local data line pairs, each of the plurality of local data line pairs comprising a first local data line and a second local data line, and the first local data line and the second local data line being configured to transmit opposite signals; and
a plurality of sense amplifiers, each of the plurality of sense amplifiers being respectively connected to one of the plurality of bit line pairs and one of the plurality of local data line pairs;
wherein two storage units positioned in the adjacent columns are respectively connected to different local data line pairs among the plurality of local data line pairs via a corresponding one of the plurality of bit line pairs and a corresponding one of the plurality of sense amplifiers.

12. The semiconductor memory according to claim 11 , further comprising:
a plurality of global data line pairs, each of the plurality of global data line pairs comprising a first global data line and a second global data line, and each of the plurality of global data line pairs respectively corresponding to the plurality of local data line pairs; and
a plurality of read-write conversion ci

Assignees

• Changxin Memory Tech Inc

Inventors

• Shang Weibing
• Li Hongwen
• Ji Kangling

Classifications

• G06F3/0655 Primary

  Vertical data movement, i.e. input-output transfer; data movement between one or more hosts and one or more storage devices · CPC title

• G06F3/0604

  Improving or facilitating administration, e.g. storage management · CPC title

• G06F3/0673

  Single storage device · CPC title

• G11C7/1006

  Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor · CPC title

• G11C11/4076 Primary

  Timing circuits (for regeneration management G11C11/406) · CPC title