Display substrate and method for manufacturing the same, driving method and display device

Patent metadata

Field	Value
Publication number	US-11877482-B2
Application number	US-201916971550-A
Country	US
Kind code	B2
Filing date	Oct 29, 2019
Priority date	Oct 29, 2019
Publication date	Jan 16, 2024
Grant date	Jan 16, 2024

Abstract

The present disclosure provides a display substrate, a method for manufacturing the same, a driving method and a display device. The display substrate includes a base substrate, gate lines, data lines and sub-pixels. The sub-pixels include sub-pixel columns corresponding to the data lines in a one-to-one manner. In a sub-pixel driving circuit of the sub-pixel, a driving transistor and a data writing transistor are located at a first side of an aperture area of the sub-pixel; a sensing transistor is located at a second side of the aperture area of the sub-pixel. The first side and the second side are opposite sides of the aperture area along the extension direction of the data lines. Gate electrodes of sensing transistors in a same sub-pixel row, and gate electrodes of data writing transistors in an adjacent next sub-pixel row, are all coupled to a gate line corresponding to the adjacent next sub-pixel row. There is a first overlapping area between an orthographic projection of a first electrode plate of the storage capacitor to the base substrate and an orthographic projection of a second electrode plate of the storage capacitor to the base substrate; an orthographic projection of the first overlapping area to the base substrate at least partially overlaps an orthographic projection of the corresponding aperture area of the sub-pixel.

First claim

What is claimed is:

1. A display substrate, comprising:
a base substrate;
a plurality of gate lines on the base substrate;
a plurality of data lines on the base substrate; and
a plurality of sub-pixels on the base substrate;
wherein the plurality of gate lines and the plurality of data lines are arranged to cross each other;
the plurality of sub-pixels include a plurality of sub-pixel columns that are corresponding to the plurality of data lines in a one-to-one manner; each of the plurality of sub-pixel columns includes a plurality of the sub-pixels arranged along an extension direction of the plurality of data lines;
the plurality of sub-pixels further include a plurality of sub-pixel rows that are corresponding to the plurality of gate lines in a one-to-one manner; each of the plurality of sub-pixel rows includes a plurality of the sub-pixels arranged along an extension direction of the plurality of gate lines;
each of the plurality of sub-pixels includes a sub-pixel driving circuit; the sub-pixel driving circuit includes a driving transistor, a data writing transistor and a sensing transistor; the driving transistor and the data writing transistor are located at a first side of an aperture area of the each of the plurality of sub-pixels; the sensing transistor is located at a second side of the aperture area of the each of the plurality of sub-pixels; the first side and the second side are opposite sides of the aperture area along the extension direction of the plurality of data lines;
a second electrode of the data writing transistor is coupled to a corresponding data line of the plurality of data lines; gate electrodes of sensing transistors in a same sub-pixel row of the plurality of sub-pixel rows, and gate electrodes of data writing transistors in an adjacent next sub-pixel row of the plurality of sub-pixel rows, are all coupled to a gate line of the plurality of gate lines corresponding to the adjacent next sub-pixel row;
the sub-pixel driving circuit further includes a storage capacitor coupled between a gate electrode of the driving transistor and a first electrode of the driving transistor; the storage capacitor includes a first electrode plate and a second electrode plate which are disposed oppositely; there is a first overlapping area between an orthographic projection of the first electrode plate to the base substrate and an orthographic projection of the second electrode plate to the base substrate; an orthographic projection of the first overlapping area to the base substrate at least partially overlaps an orthographic projection of the corresponding aperture area of the each of the plurality of sub-pixels.

2. The display substrate according to claim 1 , wherein a first electrode of the data writing transistor is located at a third side of a gate line of the plurality of gate lines corresponding to the sub-pixel row where the data writing transistor is located; the second electrode of the data writing transistor is located at a fourth side of the gate line of the plurality of gate lines corresponding to the sub-pixel row where the data writing transistor is located; the third side and the fourth side are opposite along the extension direction of the plurality of data lines; an orthographic projection of a channel portion of the data writing transistor to the base substrate is located within an orthographic projection of the gate line of the plurality of gate lines corresponding to the sub-pixel row where the data writing transistor is located, to the base substrate;
a first electrode of the sensing transistor is located at a third side of a gate line of the plurality of gate lines corresponding to a next sub-pixel row adjacent the sensing transistor;
a second electrode of the sensing transistor is located at a fourth side of the gate line of the plurality of gate lines corresponding to the next sub-pixel row adjacent the sensing transistor; an orthographic projection of a channel portion of the sensing transistor to the base substrate is located with an orthographic projection of the gate line of the plurality of gate lines corresponding to the next sub-pixel row adjacent the sensing transistor to the base substrate;
each of the plurality of gate lines is simultaneously reused as the gate electrodes of various data writing transistors in the corresponding sub-pixel row, and the gate electrodes of the sensing transistors in a preceding sub-pixel row adjacent the corresponding sub-pixel row.

3. The display substrate according to claim 1 , wherein the first electrode plate of the storage capacitor includes a first transparent electrode plate, and the second electrode plate of the storage capacitor includes a second transparent electrode plate;
the sub-pixel driving circuit further includes a first conductive connection portion;
a first end of the first conductive connection portion is coupled to the first electrode of the driving transistor; a second end of the first conductive connection portion is coupled to the second electrode of the sensing transistor;
the first conductive connection portion is reused as the second transparent electrode plate.

4. The display substrate according to claim 3 , wherein the display substrate further includes a buffer layer disposed on a surface of the base substrate; the first transparent electrode plate of the storage capacitor is located between the buffer layer and the base substrate; the second transparent electrode plate of the storage capacitor is located on a surface of the buffer layer facing away from the base substrate.

5. The display substrate according to claim 4 , wherein there is a fifth overlapping area between the orthographic projection of the first overlapping area to the base substrate and the orthographic projection of the corresponding aperture area of the each of the plurality of sub-pixels; an area of the fifth overlapping area is ¼ to ¾ of an area of the corresponding aperture area of the each of the plurality of sub-pixels.

6. The display substrate according to claim 3 , wherein the first conductive connection portion, the first electrode of the driving transistor and the second electrode of the sensing transistor are arranged in a same layer, and are all made of transparent oxide conductive material.

7. The display substrate according to claim 3 , wherein the sub-pixel driving circuit further includes a second conductive connection portion;
the second conductive connection portion is coupled to the first electrode of the data writing transistor, the first transparent electrode plate and the gate electrode of the driving transistor, respectively.

8. The display substrate according to claim 7 , wherein there is a second overlapping area between an orthographic projection of the second conductive connection portion to the base substrate and an orthographic projection of the gate electrode of the driving transistor to the base substrate; the second conductive connection portion is coupled to the gate electrode of the driving transistor through a first via hole in the second overlapping area;
there is a third overlapping area between the orthographic projection of the second conductive connection portion to the base substrate and an orthographic projection of the first electrode of the data writing transistor to the base substrate; the second conductive connection portion is coupled to the first electrode of the data writing transistor through a second via hole in the third overlapping area;
there is a fourth overlapping area between the orthographic projection of the second conductive connection portion to the base substrate and an orthographic projection of the first transparent electrode plate to the base substrate; the second conductive connection portion is coupled to the first

Assignees

• Hefei Boe Joint Tech Co Ltd
• Boe Technology Group Co Ltd

Inventors

• Yuan Can
• Li Yongqian
• Yuan Zhidong

Classifications

• H10K59/131 Primary

  Interconnections, e.g. wiring lines or terminals · CPC title

• G09G3/3208

  organic, e.g. using organic light-emitting diodes [OLED] · CPC title

• H10K71/00

  Manufacture or treatment specially adapted for the organic devices covered by this subclass · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2300/0426

  Layout of electrodes and connections · CPC title