Integrated assemblies and semiconductor memory devices

Patent metadata

Field	Value
Publication number	US-11877445-B2
Application number	US-202117150020-A
Country	US
Kind code	B2
Filing date	Jan 15, 2021
Priority date	Jan 15, 2021
Publication date	Jan 16, 2024
Grant date	Jan 16, 2024

Abstract

Some embodiments include an integrated assembly having a CMOS region. Fins extend across the CMOS region and are on a first pitch. A circuit arrangement is associated with the CMOS region and includes segments of one or more of the fins. The circuit arrangement has a first dimension along a first direction. A second region is proximate the CMOS region. Conductive structures are associated with the second region. The conductive structures extend along a second direction different than the first direction. Some of the conductive structures are electrically coupled with the circuit arrangement. The conductive structures are on a second pitch different from the first pitch. A second dimension is a distance across said some of the conductive structures along the first direction, and the second dimension is substantially the same as the first dimension.

First claim

We claim:

1. An integrated assembly, comprising:
a CMOS region;
fins extending across the CMOS region, the fins being on a first pitch;
a circuit arrangement associated with the CMOS region and comprising segments of one or more of the fins; the circuit arrangement having a first dimension along a first direction;
a second region proximate the CMOS region; and
conductive structures associated with the second region and extending along a second direction substantially orthogonal to the first direction; some of the conductive structures being electrically coupled with the circuit arrangement; the conductive structures being on a second pitch different from the first pitch; a second dimension being a distance across said some of the conductive structures along the first direction; the conductive structures being aligned with the circuit arrangement such that the second dimension is substantially the same as the first dimension.

2. The integrated assembly of claim 1 wherein the fins extend along the first direction.

3. The integrated assembly of claim 1 wherein the fins extend along the second direction.

4. The integrated assembly of claim 1 wherein the conductive structures are wordlines.

5. The integrated assembly of claim 1 wherein the conductive structures are digit lines.

6. The integrated assembly of claim 1 wherein the circuit arrangement comprises one or more WORDLINE DRIVERS.

7. The integrated assembly of claim 1 wherein the circuit arrangement comprises one or more SENSE AMPLIFIERS.

8. The integrated assembly of claim 1 wherein the second region is laterally offset relative to the CMOS region.

9. The integrated assembly of claim 1 wherein the second region is vertically offset relative to the CMOS region.

10. The integrated assembly of claim 9 wherein the second region is directly over the CMOS region.

11. The integrated assembly of claim 1 wherein the only of the conductive structures within said second dimension are said some of the conductive structures that are electrically coupled with the circuit arrangement.

12. The integrated assembly of claim 1 wherein another of the conductive structures is within said second dimension in addition to said some of the conductive structures that are electrically coupled with the circuit arrangement.

13. An integrated assembly, comprising:
a CMOS region;
fins associated with the CMOS region;
circuit arrangements associated with the CMOS region and comprising segments of one or more of the fins; the circuit arrangements comprising a first circuit arrangement and a second circuit arrangement;
a memory region proximate the CMOS region and comprising two intersecting sets of conductive lines; the conductive lines of one of the sets being wordlines and the conductive lines of the other of the sets being digit lines; the wordlines extending along a first direction, and the digit lines extending along a second direction which is substantially orthogonal to the first direction;
the first circuit arrangement having a first dimension along the first direction, and the second circuit arrangement having a second dimension along the second direction;
some of the wordlines being coupled with the second circuit arrangement and some of the digit lines being coupled with the first circuit arrangement; a third dimension being along the second direction and being a distance across all of the wordlines that are coupled with the second circuit arrangement, and a fourth dimension being along the first direction and being a distance across all of the digit lines that are coupled with the first circuit arrangement;
the wordlines being aligned with the second circuit arrangement such that the third dimension is substantially the same as the second dimension; and
the digit lines being aligned with the first circuit arrangement such that the fourth dimension is substantially the same as the first dimension.

14. The integrated assembly of claim 13 wherein the first circuit arrangement includes one or more SENSE AMPLIFIERS.

15. The integrated assembly of claim 13 wherein the second circuit arrangement includes one or more WORDLINE DRIVERS.

16. The integrated assembly of claim 13 wherein the memory region is laterally offset relative to the CMOS region.

17. The integrated assembly of claim 13 wherein the memory region is vertically offset relative to the CMOS region.

18. The integrated assembly of claim 17 wherein the memory region is directly over the CMOS region.

19. The integrated assembly of claim 13 wherein the fins have substantially the same pitch across the first and second circuit arrangements.

20. The integrated assembly of claim 13 wherein the fins have a different pitch across the first circuit arrangement than across the second circuit arrangement.

21. The integrated assembly of claim 20 comprising a buffer region between the first and second circuit arrangements.

22. The integrated assembly of claim 21 wherein at least a portion of said buffer region lacks the fins.

23. The integrated assembly of claim 13 wherein the fins are on a first pitch, the digit lines are on a second pitch and the wordlines are on a third pitch; and wherein the first pitch is different relative to the second and third pitches.

24. The integrated assembly of claim 23 wherein the second and third pitches are smaller than the first pitch.

25. The integrated assembly of claim 23 wherein the second pitch is substantially the same as the third pitch.

26. An integrated assembly, comprising:
a semiconductor base;
a CMOS region associated with the base;
fins extending across the CMOS region and being on a first pitch;
circuit arrangements associated with the CMOS region and comprising segments of one or more of the fins; the circuit arrangements comprising a WORDLINE DRIVER arrangement and a SENSE AMPLIFIER arrangement;
a memory deck over the base;
wordlines and digit lines associated with the memory deck; the wordlines extending along a first direction, and the digit lines extending along a second direction which is substantially orthogonal to the first direction; the wordlines being on a second pitch and the digit lines being on a third pitch; the second and third pitches being different than the first pitch;
the SENSE AMPLIFIER arrangement having a first dimension along the first direction, and the WORDLINE DRIVER arrangement having a second dimension along the second direction;
some of the wordlines being coupled with the WORDLINE DRIVER arrangement and some of the digit lines being coupled with the SENSE AMPLIFIER arrangement; a third dimension being along the second direction and being a distance across all of the wordlines that are coupled with the WORDLINE DRIVER arrangement, and a fourth dimension being along the first direction and being a distance across all of the digit lines that are coupled with the SENSE AMPLIFIER arrangement;
the wordlines being aligned with the WORDLINE DRIVER arrangement such that the third dimension is substantially the same as the second dimension; and
the digit lines being aligned with the SENSE AMPLIFIER arrangement such that the fourth dimension is substantially the same as the first dimension.

27. The integrated assembly of claim 26 wherein said some of the digit lines that are coupled with the SENSE AMPLIFIER arrangement are first digit lines, and alternate with second digit lines which are n

Assignees

• Micron Technology Inc

Inventors

• Hwang Sangmin
• Lee Kyuseok
• Wieduwilt Christopher G

Classifications

• H10D84/853

  comprising FinFETs · CPC title

• H10D30/62

  Fin field-effect transistors [FinFET] · CPC title

• H10B12/50 Primary

  Peripheral circuit region structures · CPC title

• G11C5/063

  Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay · CPC title

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title