Hybrid analog/digital equalizer architecture for high-speed receiver

Patent metadata

Field	Value
Publication number	US-11876649-B2
Application number	US-202217648440-A
Country	US
Kind code	B2
Filing date	Jan 20, 2022
Priority date	Aug 6, 2021
Publication date	Jan 16, 2024
Grant date	Jan 16, 2024

Abstract

Equalization circuitry for a data channel in an integrated circuit device includes an analog equalization stage coupled to the data channel, and a digital signal processing stage downstream of the analog equalization stage. The digital signal processing stage generates control signals to control the analog equalization stage, and includes a digital equalization stage that operates on output of the analog equalization stage. The analog equalization stage may further include an enhanced processing stage for optical signals, which may be selectably coupled to the analog equalization stage. The analog equalization stage may include at least one feed-forward or feedback equalization stage, and a decision stage that outputs decision signals at one of a first plurality of signal levels. The enhanced processing stage operates on the decision signals to output enhanced decision signals at one of a second plurality of signal levels of higher resolution than the first plurality of signal levels.

First claim

What is claimed is:

1. Equalization circuitry for a data channel in an integrated circuit device, the equalization circuitry comprising:
an analog equalization circuitry portion coupled to the data channel, including interleaver circuitry configured to disperse incoming signals to a plurality of interleaved equalization blocks, each interleaved equalization block in the plurality of equalization blocks comprising a feed-forward equalization circuitry portion, a decision-feedback equalization circuitry portion and a decision circuitry portion; and
a digital signal processing circuitry portion downstream of the analog equalization circuitry portion, the digital signal processing circuitry portion being configured to generate control signals to control the analog equalization circuitry portion, the digital signal processing circuitry portion also including a digital equalization circuitry portion configured to operate on an output of the analog equalization circuitry portion; wherein:
each respective interleaved equalization block in the plurality of equalization blocks comprises a probe slicer configured to output estimated signal properties for use by the digital signal processing circuitry portion, the estimated signal properties excluding effects of analog circuitry in the respective interleaved equalization block.

2. The equalization circuitry of claim 1 wherein the analog equalization circuitry portion further comprises an enhanced processing circuitry portion for optical signals.

3. The equalization circuitry of claim 2 wherein the enhanced processing circuitry portion for optical signals is selectably coupled to the analog equalization circuitry portion.

4. The equalization circuitry of claim 3 wherein selectable coupling of the enhanced processing circuitry portion for optical signals to the analog equalization circuitry portion comprises metallization in the integrated circuit device.

5. The equalization circuitry of claim 2 wherein:
the decision circuitry portion outputs decision signals at one of a first plurality of signal levels; and
the enhanced processing circuitry portion for optical signals operates on the decision signals to output enhanced decision signals at one of a second plurality of signal levels, the second plurality of signal levels being of higher resolution than the first plurality of signal levels.

6. The equalization circuitry of claim 5 wherein the feed-forward equalization circuitry portion comprises an analog feed-forward equalization circuitry portion and the feedback equalization circuitry portion comprises an analog decision-feedback equalization circuitry portion.

7. The equalization circuitry of claim 1 wherein:
at least one of (1) the incoming signals and (2) outputs of at least one of the feed-forward equalization circuitry portion and the decision circuitry portion are configured to be input as at least one of (a) precursors to a feed-forward equalization circuitry portion of a first other interleaved equalization block in the plurality of equalization blocks, (b) post-cursors to a feed-forward equalization circuitry portion of a second other interleaved equalization block in the plurality of equalization blocks, and (c) post-cursors to a decision-feedback equalization circuitry portion of a third other interleaved equalization block in the plurality of equalization blocks.

8. The equalization circuitry of claim 7 wherein each interleaved equalization block in the plurality of equalization blocks comprises a variable gain amplifier configured to compensate for DC loss associated with the feed-forward equalization circuitry portion.

9. The equalization circuitry of claim 1 further comprising:
an analog front end upstream of the interleaver circuitry; and
feedback circuitry configured to correct DC offset at the analog front end.

10. The equalization circuitry of claim 9 wherein the feedback circuitry comprises:
a low-bandwidth feedback loop from an output of the analog front end to an input of the analog front end; and
a high-bandwidth feedback loop from an output downstream of the decision stage to an input of the analog front end.

11. A method of equalization of signals on a data channel in an integrated circuit device, the method comprising:
performing analog equalization on the signals on the data channel, including:
interleaving incoming signals to a plurality of interleaved equalization blocks;
performing, on signals in each interleaved equalization block in the plurality of equalization blocks, feed-forward equalization and decision-feedback equalization, and outputting equalization signals, and
estimating, in each respective interleaved equalization block in the plurality of equalization blocks, estimated signal properties for use in digital signal processing, the estimated signal properties excluding effects of analog processing in the respective interleaved equalization block; and
performing the digital signal processing on an output of the analog equalization, the digital signal processing including generating control signals to control the analog equalization, the digital signal processing also including digital equalization.

12. The method of claim 11 wherein performing analog equalization further comprises performing additional equalization when the signals on the data channel are optical signals.

13. The method of claim 12 wherein:
performing analog equalization further comprises outputting decision signals at one of a first plurality of signal levels; and
performing additional equalization comprises operating on the decision signals to output enhanced decision signals at one of a second plurality of signal levels, the second plurality of signal levels being of higher resolution than the first plurality of signal levels.

14. The method of claim 13 further comprises amplifying an output of the feed-forward equalization to compensate for DC loss associated with the feed-forward equalization.

15. The method of claim 11 further comprising:
inputting at least one of (1) the incoming signals and (2) the output equalization signals as inputs to at least one of (a) precursors to feed-forward equalization in a first other interleaved equalization block in the plurality of equalization blocks, (b) post-cursors to feed-forward equalization in a second other interleaved equalization block in the plurality of equalization blocks, and (c) post-cursors to decision-feedback equalization in a third other interleaved equalization block in the plurality of equalization blocks.

16. The method of claim 11 further comprising using feedback to correct DC offset of an analog front end upstream of the interleaved equalization blocks.

17. The method of claim 16 wherein using feedback comprises:
feeding back low-bandwidth signals from an output of the analog front end to an input of the analog front end to correct device-mismatch-induced DC offset in the analog front end; and
feeding back high-bandwidth signals from an output downstream of the decision signals to an input of the analog front end to correct offset caused by one or both of baseline wander and low-frequency impairment.

Assignees

• Marvell Asia Pte Ltd

Inventors

• Wang Luke
• Smith Benjamin
• Alnabulsi Basel
• Dallaire Stephane
• Forey Simon
• Raviprakash Karthik
• Prabha Praveen
• Reyes Benjamin T

Classifications

• H04L25/03076 Primary

  not using decision feedback · CPC title

• H04L25/0232

  by interpolation between sounding signals · CPC title

• H04L2025/03433

  characterised by equaliser structure · CPC title

• H04L2025/03605

  Block algorithms · CPC title

• H04L25/03019 Primary

  adaptive, i.e. capable of adjustment during data reception · CPC title