Current to digital converter circuit, optical front end circuit, computed tomography apparatus and method

Patent metadata

Field	Value
Publication number	US-11876539-B2
Application number	US-202017637186-A
Country	US
Kind code	B2
Filing date	Aug 20, 2020
Priority date	Aug 22, 2019
Publication date	Jan 16, 2024
Grant date	Jan 16, 2024

Abstract

A current to digital converter circuit has an integrator amplifier with an input adapted to receive a current signal and an output adapted to provide a voltage signal as a function of an integration of the current signal, a quantizer circuit with an input which is coupled to the output of the integrator amplifier and with an output adapted to provide a binary result signal as a function of a comparison of the voltage signal with at least a first reference voltage signal, a digital-to-analog converter circuit which is coupled in a switchable manner as a function of the binary result signal to the input of the integrator amplifier, and a controlled current source which is coupled to the output of the integrator amplifier via a first switch which is controlled as a function of the binary result signal such that an auxiliary current is supplied to the output of the integrator amplifier.

First claim

The invention claimed is:

1. A current to digital converter circuit having
an integrator amplifier with an input adapted to receive a current signal and an output adapted to provide a voltage signal as a function of an integration of the current signal,
a quantizer circuit with an input which is coupled to the output of the integrator amplifier and with an output adapted to provide a binary result signal as a function of a comparison of the voltage signal with at least a first reference voltage signal,
a digital-to-analog converter circuit which is coupled in a switchable manner as a function of the binary result signal to the input of the integrator amplifier, and
a controlled current source which is coupled to the output of the integrator amplifier via a first switch which is controlled as a function of the binary result signal such that an auxiliary current is supplied to the output of the integrator amplifier.

2. The current to digital converter circuit according to claim 1 ,
wherein the auxiliary current is supplied upon occurrence of an impulse of the binary result signal for an amount of time which is smaller than a time constant realized by the integrator amplifier.

3. The current to digital converter circuit according claim 1 ,
wherein the controlled current source comprises a current generation unit and a timing generation unit, wherein the timing generation unit is prepared to provide a charging clock signal, wherein a first level change of the charging clock signal is generated upon occurrence of a level change of the binary result signal and a second level change of the charging clock signal is generated as soon as charging of an auxiliary capacitor comprised by the timing generation unit by means of a bias current has reached a level of a second reference voltage, and
wherein the current generation unit is prepared to provide the auxiliary current and comprises either a current mirror component for mirroring the bias current or an adjustable resistor which is connected to a supply potential.

4. The current to digital converter circuit according to claim 1 ,
further comprising a control unit which is prepared to provide a main clock signal for controlling operation of at least the quantizer circuit.

5. The current to digital converter circuit according to claim 1 ,
wherein the integrator amplifier comprises an operational amplifier and an integration capacitor which is coupled in a feedback loop of the operational amplifier between its output and its inverting input, wherein the operational amplifier is realized by a folded cascode wherein each folding node of the folded cascode is implemented by a transistor.

6. The current to digital converter circuit according to claim 5 ,
wherein the operational amplifier is realized by two or more stages.

7. The current to digital converter circuit according to claim 1 ,
wherein the digital-to-analog converter circuit is realized as a one-bit digital-to-analog converter on the basis of a switched capacitor which is additionally connected in a switchable manner to respective terminals for supplying a third reference voltage.

8. The current to digital converter circuit according to claim 1 ,
wherein the digital-to-analog converter circuit is realized as an M bit digital-to-analog converter on the basis of multiple capacitors, wherein M is an integer greater than or equal to two.

9. The current to digital converter circuit according to claim 7 ,
wherein the quantizer circuit is realized as a clocked comparator amplifier for exactly one bit.

10. The current to digital converter circuit according to claim 8 ,
wherein the quantizer circuit is realized as a clocked quantizer for M bit.

11. An optical front end circuit comprising
the current to digital converter circuit according to claim 4 , wherein the current signal at the input of the integrator amplifier comprises a photocurrent of a photodiode which can be connected to said input,
a sampling capacitor which is coupled to the output of the integrator amplifier via a second switch, the second switch being controlled by a sampling clock signal,
an analog-to-digital converter, ADC, circuit which is coupled by its input to the sampling capacitor via a third switch, the third switch being controlled by a conversion clock signal, the ADC circuit having an output at which a digital signal is provided, wherein the digital signal is a function of the current signal and comprises N bit, wherein N is an integer greater than or equal to one, and
a calculation circuit which is coupled to the output of the ADC circuit and to an output of the quantizer circuit, the calculation circuit being prepared to provide a digital word signal by combining the binary result signal with the digital signal.

12. The optical front end circuit according to claim 11 ,
wherein the control unit is prepared to provide the sampling clock signal and the conversion clock signal both in dependence on the main clock signal, the sampling clock signal and the conversion clock signal having different clock rates or basically equal clock rates.

13. The optical front end circuit according to claim 11 ,
wherein the calculation circuit is prepared to provide the digital word signal as a correlated double-sample.

14. A computed tomography apparatus having an optical front end circuit according to claim 11 .

15. A method for providing an output voltage comprising at least the following steps:
supplying a current signal,
converting the current signal into a voltage signal by means of charge integration in an integrator amplifier,
quantizing the voltage signal and therefrom providing a binary result signal having at least one bit,
upon provision of the binary result signal basically concurrently providing an auxiliary current to an output of the integrator amplifier for recharging said output and adding an additional amount of charge in function of the binary result signal to the current signal.

Assignees

• Ams Int Ag

Inventors

• Kanagal Ramesh Srinidhi Koushik
• Fröhlich Thomas

Classifications

• H03M3/412 Primary

  characterised by the number of quantisers and their type and resolution · CPC title

• H03F3/45475

  using IC blocks as the active amplifying circuit · CPC title

• H03M1/18

  Automatic control for modifying the range of signals the converter can handle, e.g. gain ranging · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title

• H03F2200/18

  the bias of the gate of a FET being controlled by a control signal · CPC title