Digital-to-analog converter (DAC) distortion pre-compensation

Patent metadata

Field	Value
Publication number	US-11876525-B2
Application number	US-202217741152-A
Country	US
Kind code	B2
Filing date	May 10, 2022
Priority date	May 10, 2022
Publication date	Jan 16, 2024
Grant date	Jan 16, 2024

Abstract

An apparatus comprises circuitry configured to generate a predicted error signal by applying to a digital signal a distortion model characterized by parameters configured to model circuit component mismatches in a digital-to-analog converter (DAC), circuitry configured to generate a pre-compensated digital signal using the digital signal and the predicted error signal, and circuitry configured to provide the pre-compensated digital signal to the DAC for conversion into an analog signal.

First claim

What is claimed is:

1. An apparatus comprising:
circuitry configured to generate a predicted error signal by applying to a digital signal a distortion model characterized by parameters configured to model circuit component mismatches in a digital-to-analog converter (DAC);
circuitry configured to generate a pre-compensated digital signal using the digital signal and the predicted error signal; and
circuitry configured to provide the pre-compensated digital signal to the DAC for conversion into an analog signal,
wherein the DAC comprises a plurality of weighted current sources, and wherein the circuit component mismatches comprise one or more of
rise/fall asymmetry between currents flowing from the weighted current sources; and
timing offsets of OFF-to-ON and ON-to-OFF transitions between currents flowing from the weighted current sources.

2. The apparatus as claimed in claim 1 , wherein the circuit component mismatches further comprise
amplitude mismatches between currents flowing from the weighted current sources.

3. The apparatus as claimed in claim 1 , wherein the distortion model comprises a plurality of detectors, each detector configured to detect sequences of J bits in the digital signal, wherein J≥2, and wherein each bit is selected from 0 and 1.

4. The apparatus as claimed in claim 3 , wherein J=3.

5. The apparatus as claimed in claim 1 , wherein the distortion model is further characterized by a bias term configured to correct for predicted tones in the analog signal.

6. The apparatus as claimed in claim 1 , wherein the pre-compensated digital signal comprises N bits per sample, wherein the digital signal comprises more than N bits per sample, and wherein N is a positive integer.

7. The apparatus as claimed in claim 6 , wherein the circuitry is configured to apply the distortion model at a resolution of N bits per sample.

8. The apparatus as claimed in claim 1 , wherein the DAC comprises a plurality of weighted current sources, and wherein a weight ratio of at least one pair of the weighted current sources is a positive real number different from an integer power of two.

9. An apparatus comprising:
circuitry configured to generate a predicted error signal by applying to a digital signal a distortion model characterized by parameters configured to model circuit component mismatches in a digital-to-analog converter (DAC), wherein the parameters comprise coefficients of a plurality of finite impulse response (FIR) filters;
circuitry configured to generate a pre-compensated digital signal using the digital signal and the predicted error signal; and
circuitry configured to provide the pre-compensated digital signal to the DAC for conversion into an analog signal.

10. An apparatus comprising:
circuitry configured to generate a predicted error signal by applying to a digital signal a distortion model characterized by parameters configured to model circuit component mismatches in a digital-to-analog converter (DAC);
circuitry configured to generate a pre-compensated digital signal using the digital signal and the predicted error signal, wherein the pre-compensated digital signal is generated based on a difference between the digital signal and the predicted error signal; and
circuitry configured to provide the pre-compensated digital signal to the DAC for conversion into an analog signal.

Assignees

• Babaee Ramin
• Oveis Gharan Shahab
• Bouchard Martin
• Ciena Corp

Inventors

• Babaee Ramin
• Oveis Gharan Shahab
• Bouchard Martin

Classifications

• H03M1/0602 Primary

  of deviations from the desired transfer characteristic (H03M1/0617 takes precedence) · CPC title

• H03M1/1042 Primary

  the look-up table containing corrected values for replacing the original digital values (H03M1/1052 takes precedence) · CPC title

• H03M1/742

  using current sources as quantisation value generators · CPC title