Oscillator using sampling PLL-based injection

Patent metadata

Field	Value
Publication number	US-11876487-B2
Application number	US-202318152418-A
Country	US
Kind code	B2
Filing date	Jan 10, 2023
Priority date	Mar 8, 2022
Publication date	Jan 16, 2024
Grant date	Jan 16, 2024

Abstract

An oscillator includes a crystal oscillation circuit configured to generate an oscillation signal having a natural frequency, an injection circuit configured to inject a first injection signal and a second injection signal into the crystal oscillation circuit, a dithering circuit configured to transmit a first control signal for generating the first injection signal to the injection circuit, and a phased-lock loop (PLL) circuit configured to lock a phase of the first injection signal to the natural frequency, to transmit a second control signal for generating the second injection signal to the injection circuit.

First claim

What is claimed is:

1. An oscillator comprising:
a crystal oscillation circuit configured to generate an oscillation signal having a natural frequency;
an injection circuit configured to inject a first injection signal and a second injection signal having a different frequency from the first injection signal into the crystal oscillation circuit;
a dithering circuit configured to transmit a first control signal for generating the first injection signal to the injection circuit; and
a phased-lock loop (PLL) circuit configured to lock a phase of the first injection signal to the natural frequency, to transmit a second control signal for generating the second injection signal to the injection circuit.

2. The oscillator of claim 1 , wherein
the oscillation signal has a first swing voltage when the first injection signal is injected, and
the oscillation signal has a second swing voltage that is greater than the first swing voltage when the second injection signal is injected.

3. The oscillator of claim 1 , wherein
the injection circuit is configured to inject the first injection signal based on the first control signal, and
the injection circuit is configured to inject the second injection signal based on the second control signal, after injecting the first injection signal.

4. The oscillator of claim 1 , wherein the injection circuit includes:
a voltage controlled oscillator configured to generate the first injection signal based on the first control signal, to generate the second injection signal based on the second control signal; and
a switching unit connected to the crystal oscillation circuit to inject the first injection signal and the second injection signal into the crystal oscillation circuit according to a switching operation.

5. The oscillator of claim 4 , wherein the dithering circuit includes:
a divider configured to divide a free-running frequency of the voltage controlled oscillator to generate a dithering signal having a specific frequency width;
an alternating current (AC)-coupling circuit configured to AC-couple the dithering signal;
a first switch connected to the AC-coupling circuit to pass the dithering signal according to a switching operation;
a direct current (DC)-coupling circuit connected to the first switch to DC-couple a temperature proportional voltage proportional to an absolute temperature of the voltage controlled oscillator, and bias the dithering signal to the temperature proportional voltage; and
a second switch connected to the AC-coupling circuit and the DC-coupling circuit to pass the dithering signal biased to the temperature proportional voltage according to a switching operation.

6. The oscillator of claim 5 , wherein the dithering circuit further includes:
a gain adjustment unit connected to the voltage controlled oscillator and the PLL circuit to control a loop gain of the PLL circuit based on the first injection signal.

7. The oscillator of claim 4 , wherein the voltage controlled oscillator includes a ring voltage controlled oscillator including a plurality of delay cells.

8. The oscillator of claim 1 , wherein the PLL circuit is configured to sample the oscillation signal to obtain a sampling voltage, compare the sampling voltage with a reference voltage, and adjust the second control signal until the sampling voltage reaches the reference voltage.

9. The oscillator of claim 8 , wherein the PLL circuit includes:
a first switch connected to the injection circuit to pass the first injection signal according to a switching operation;
a sampling circuit connected to the first switch and the crystal oscillation circuit, the sampling circuit configured to sample the oscillation signal based on the first injection signal to obtain the sampling voltage;
a reference voltage providing circuit configured to provide the reference voltage;
a transconductance cell configured to compare the sampling voltage with the reference voltage to generate the second control signal according to a comparison result; and
a second switch configured to pass the second control signal according to a switching operation.

10. The oscillator of claim 9 , wherein the sampling circuit includes:
a sample and hold circuit including a third switch configured to perform a switching operation according to the first injection signal and a capacitor; and
a dummy circuit connected to the sample and hold circuit to have a differential structure.

11. The oscillator of claim 9 , wherein the phase of the first injection signal is locked to the natural frequency when the sampling voltage reaches the reference voltage.

12. An electronic device comprising:
an oscillator configured to generate an oscillation signal having a natural frequency by injecting a first injection signal and a second injection signal through a first phase, a second phase, a third phase and a fourth phase; and
a finite state machine (FSM) configured to control the oscillator in the first to fourth phases,
wherein the oscillator includes
a crystal oscillation circuit configured to generate the oscillation signal,
an injection circuit configured to inject the first injection signal and the second injection signal into the crystal oscillation circuit in each of the first and fourth phases,
a dithering circuit configured to transmit a first control signal for generating the first injection signal to the injection circuit in the first phase and the second phase, and
a phased-lock loop (PLL) circuit configured to lock a phase of the first injection signal to the natural frequency in the third phase, to transmit a second control signal for generating the second injection signal to the injection circuit.

13. The electronic device of claim 12 , wherein
the oscillation signal has a first swing voltage in the second and third phases, and
the oscillation signal has a second swing voltage that is greater than the first swing voltage after the fourth phase.

14. The electronic device of claim 12 , wherein the injection circuit includes:
a voltage controlled oscillator configured to generate the first injection signal based on the first control signal, and to generate the second injection signal based on the second control signal; and
a switching unit connected to the crystal oscillation circuit, the switching unit configured to inject the first injection signal and the second injection signal into the crystal oscillation circuit in the first and fourth phases according to the FSM.

15. The electronic device of claim 14 , wherein the dithering circuit includes:
a divider configured to divide a free-running frequency of the voltage controlled oscillator to generate a dithering signal;
an alternating current (AC)-coupling circuit configured to AC-couple the dithering signal;
a first switch connected to the AC-coupling circuit and configured to pass the dithering signal in the first phase according to the FSM;
a direct current (DC)-coupling circuit connected to the first switch to DC-couple a temperature proportional voltage proportional to an absolute temperature of the voltage controlled oscillator, and bias the dithering signal to the temperature proportional voltage; and
a second switch connected to the AC-coupling circuit and the DC-coupling circuit and configured to pass the dithering signal biased to the temperature proportional voltage in the first and second phases according to the FSM.

16. The electronic device of claim 15 , wherein a voltage of the first control signal is equal to the temperature proportional voltage in the second phase.

17. The electronic device of

Assignees

• Samsung Electronics Co Ltd

Inventors

• Jung Jaehong
• Kim Seungjin
• Oh Seunghyun

Classifications

• H03B5/36 Primary

  active element in amplifier being semiconductor device ({H03B5/323, H03B5/326} , H03B5/38 take precedence) · CPC title

• H03L7/099

  concerning mainly the controlled oscillator of the loop · CPC title

• H03B2200/009

  Reduction of phase noise · CPC title

• H03B5/362 Primary

  the amplifier being a single transistor (H03B5/364 - H03B5/368 take precedence) · CPC title

• H03B2200/0074

  Locking of an oscillator by injecting an input signal directly into the oscillator · CPC title