ESD protection circuit

Patent metadata

Field	Value
Publication number	US-11876090-B2
Application number	US-202217989481-A
Country	US
Kind code	B2
Filing date	Nov 17, 2022
Priority date	Sep 14, 2021
Publication date	Jan 16, 2024
Grant date	Jan 16, 2024

Abstract

An electrostatic discharge protection circuit capable of clamping both positive and negative ESD events and passing signals is provided. Generally, the circuit includes a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected, the PFET clamp including a plurality of PFETs in a DN-well, an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and a bias network for biasing a voltage of the DN well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and to ground potential when the pin voltage is less than ground potential. The plurality of are PFETs coupled in parallel between the pin and the NFET clamp, each of the PFETs is coupled to the pin though one of a plurality ballast resistors.

First claim

What is claimed is:

1. An intelligent battery sensor (IBS) comprising:
a communication circuit; and
an electrostatic discharge (ESD) protection circuit comprising:
a p-channel field-effect transistor (PFET) clamp coupled to a pin to be protected from positive and negative ESD events, the PFET clamp including a plurality of PFETs in a first DN-well,
an n-channel field-effect transistors (NFET) clamp coupled between ground and the pin through the PFET clamp, the NFET clamp including a plurality of NFETs coupled in series, and
a bias network for biasing a voltage of the DN-well to substantially equal a voltage on the pin when the voltage on the pin is greater than ground potential, and equal to ground potential when the voltage of the pin is less than ground potential,
wherein the plurality of PFETs are coupled in parallel between the pin and the NFET clamp, each of the plurality of PFETs coupled to the pin through one of a plurality of ballast resistors.

2. The IBS of claim 1 , wherein the bias network comprises a voltage Higher-Driver (V Higher-Driver ) node between the PFET clamp and the NFET clamp through which the first DN-well is biased, and wherein the V Higher-Driver node is coupled to an internal signal node in an integrated-circuit (IC) including the ESD protection circuit to pass signals to and from the pin into the IC through the PFET clamp and the V Higher-Driver node.

3. The IBS of claim 2 , wherein the bias network further comprises a higher-of-two-voltages circuit (higher-circuit) having a first input coupled to ground, second input coupled to the pin, and an output node coupled to the V Higher-Driver node, and wherein the higher-circuit is configured to couple a higher of a voltage on the first input or the second input to the output node.

4. The IBS of claim 3 , wherein the higher-circuit comprises a cascoded pair of a first and a second DN-well biasing transistors coupled between the V Higher-Driver node, and through a limiting resistor, to ground, wherein a gate of the first DN-well biasing transistor is coupled to the pin through a high impedance resistor, and a gate of the second DN-well biasing transistor is coupled to the pin through a voltage divider coupled between the pin and ground.

5. The IBS of claim 4 further comprising a shut-off acceleration transistor coupled between a gate node (7 node) of the plurality of PFETs of the PFET clamp and the V Higher-Driver node to shut off the plurality of PFETs when a voltage on the pin is less than ground potential.

6. The IBS of claim 1 , wherein the NFET clamp comprises:
an isolated NFET coupled to the PFET clamp, and having an n+ source isolated from a body of the isolated NFET by a source P-well and by a second DN-well surrounding the source P-well; and
a non-isolated NFET coupled in series between the isolated NFET and ground, and having an n+ source which is not isolated from a body of the non-isolated NFET but is formed in a source P-well in a p-type substrate.

7. The IBS of claim 1 , wherein the ESD protection circuit is part of the communication circuit.

8. The IBS of claim 1 , wherein the IBS is coupled to a positive terminal of a battery in an automobile, and, across a shunt resistor coupled between a negative terminal of the battery and a chassis ground.

9. The IBS of claim 1 , wherein at least one of the plurality of PFETs comprises:
a gate overlying a channel region in a -type substrate;
a p+ source;
a p+ drain; and
a body contact, wherein the gate, the p+ source, the p+ drain and the body contact are separated by a plurality of isolation structures.

10. The IBS of claim 9 , wherein:
the p+ source and the body contact are formed in an N-well on a first side of the channel region;
the p+ drain is formed in a drain extension P-well on a second side of the channel region; and
an extended isolation structure partially underlying the gate.

11. The IBS of claim 1 , further comprising:
a microcontroller unit (MCU),
a digital subsystem,
at least one analog to digital converter (ADC); and
a temperature sensor,
wherein the IBS, through the MCU, the digital subsystem, the at least one ADC and the temperature sensor is for measuring at least one characteristic of a battery coupled to the IBS.

12. A sensor circuit comprising:
an electrostatic discharged (ESD) protection circuit; and
a control circuit operatively coupled to the ESD protection circuit, the control circuit for sending instructions to the ESD protection circuit, the instructions for:
coupling a plurality of p-channel field-effect transistors (PFETs) of a PFET clamp in parallel between a pin to be protected and a V Higher-Driver node in the circuit, each of the plurality of PFETs is coupled to the pin through one of a plurality of ballast resistors;
coupling an n-channel field-effect transistor (NFET) clamp between ground and the V Higher-Driver node, the NFET clamp including a pair of NFETs coupled in series;
biasing through the V Higher-Driver node a first DN-well in which the plurality of PFETs are formed to a higher of a voltage (V pin ) applied to a pin or to ground potential; and
when V pin is a positive voltage less than a positive trigger voltage, coupling an external signal from the pin through the plurality of PFETs to an internal signal node in the circuit coupled to the a V Higher-Driver node.

13. The sensor circuit of claim 12 , wherein the control circuit is further for sensing instructions to the ESD protection circuit, the instructions for, when V pin exceeds the positive trigger voltage:
pulling-up the voltage of the V Higher-Driver node to V pin ;
clamping the voltage on the V Higher-Driver node to a clamping voltage of the NFET clamp;
forward biasing source junctions of the plurality of PFETs to the first DN-well coupled to the V Higher-Driver node; and
forward biasing parasitic PNP transistors formed by the source junctions of the plurality of PFETs, the first DN-well and a substrate in which the circuit is formed,
whereby a MOSFET current through the plurality of PFETs and a parasitic current through the parasitic PNP transistors brings V pin down to the clamped voltage on the V Higher-Driver node.

14. The sensor circuit of claim 12 , wherein the control circuit is further for sensing instructions to the ESD protection circuit, the instructions for, when V pin exceeds a negative trigger voltage large enough to break down a drain junction of one or more of the plurality of PFETs pulling-down the voltage of the V Higher-Driver node to less than ground potential:
forward biasing a drain terminal of a first NFET connected to the V Higher-Driver node;
forward biasing a parasitic NPN transistor in the first NFET formed by an n+ drain junction of the first NFET, a P-well in which the n+ drain junction is formed, and a second DN-well in which the P-well is formed; and
conducting current from V Higher-Driver node through the parasitic NPN transistor and through a junction between the second DN-well and a substrate in which the circuit is formed to the substrate and to a second NFET connected between first NFET and ground, whereby the drain terminal of the first NFET is shorted to ground and a voltage of the V Higher-Driver node is substantially held to ground potential.

Assignees

• Cypress Semiconductor Corp

Inventors

• Rogers David Michael
• Mann Eric N
• Swindlehurst Eric Lee
• Miyamae Toru
• Williams Timothy John
• Nagai Ryuta
• Lee Sungkwon
• Kapre Ravindra M
• Qian Mimi Xuefeng Zhao
• Yi Yan
• Ho Dung Si
• Chin-Hua Boo

Classifications

• H10D89/911

  using passive elements as protective elements · CPC title

• H10D89/819 Primary

  Bias arrangements for gate electrodes of FETs, e.g. RC networks or voltage partitioning circuits (FETs in a Darlington configuration H10D89/817) · CPC title

• H10D89/811 Primary

  using FETs as protective elements · CPC title

• H01L27/0285 Primary

  Electricity · mapped topic

• H01L27/0288

  Electricity · mapped topic