Printed circuit board

Patent metadata

Field	Value
Publication number	US-11876004-B2
Application number	US-202217660161-A
Country	US
Kind code	B2
Filing date	Apr 21, 2022
Priority date	Sep 29, 2017
Publication date	Jan 16, 2024
Grant date	Jan 16, 2024

Abstract

A printed circuit board according to an embodiment includes: an insulating layer; a first pad disposed on a first surface of the insulating layer; a first conductive layer disposed on the first pad and including gold (Au); a second pad disposed on a second surface of the insulating layer; and a second conductive layer disposed on the second pad and including gold (Au), wherein the first conductive layer is a conductive layer connected to a wire, the second conductive layer is a conductive layer connected to a solder, and the first conductive layer is thicker than the second conductive layer.

First claim

The invention claimed is:

1. A circuit substrate comprising:
an insulating layer including a top surface and a bottom surface opposite to the top surface;
a circuit layer disposed on the insulating layer; and
a cover metal layer disposed on the circuit layer,
wherein the circuit layer includes a portion that is positioned higher than the top surface of the insulating layer with respect to the bottom surface of the insulating layer,
wherein the cover metal layer includes a cover portion that is positioned higher than or equal to the top surface of the insulating layer,
wherein the cover portion of the cover metal layer includes a first portion that is vertically overlapped with the portion of the circuit layer, and a second portion that is not vertically overlapped with the portion of the circuit metal layer,
wherein the portion of the circuit layer includes an entirely even top surface,
wherein a bottom surface of the first portion of the cover metal layer is in contact with the even top surface of the portion of the circuit layer,
wherein a top surface of the second portion includes a curved surface, and
wherein a top width of the even top surface of the portion of the circuit layer is different from a bottom width of the portion of the circuit layer that is coplanar with the top surface of the insulating layer, and
wherein the curved surface is not overlapped vertically with the portion of the circuit layer.

2. The circuit substrate of claim 1 ,
wherein the cover portion of the cover metal layer includes a connection portion disposed between the first portion of the cover portion of the cover metal layer and the second portion of the cover portion of the cover metal layer, and
wherein the connection portion of the cover portion is in contact with the circuit layer.

3. The circuit substrate of claim 2 ,
wherein the second portion is extended outward from the connecting portion, and
wherein the curved surface is bent toward the insulating layer.

4. The circuit substrate of claim 3 ,
wherein the second portion of the cover portion is not in contact with the portion of the circuit layer.

5. The circuit substrate of claim 4 , wherein a first height between a top surface of the portion of the circuit layer and the top surface of the insulating layer is greater than a second height between a bottom surface of the second portion and the top surface of the insulating layer.

6. The circuit substrate of claim 1 , comprising:
a semiconductor chip disposed on the insulating layer,
wherein the cover metal layer electrically contacts the semiconductor chip.

7. The circuit substrate of claim 5 ,
wherein the bottom surface of the second portion is not in contact with the insulating layer.

8. The circuit substrate of claim 6 ,
wherein the cover metal layer includes a material that is different from a material included in the circuit layer.

9. The circuit substrate of claim 8 ,
wherein the cover metal layer includes Au, and the circuit layer includes Cu.

10. The circuit substrate of claim 3 ,
wherein the circuit layer includes a first layer and a second layer,
wherein a top surface of the first layer faces the second layer,
wherein the top surface of first layer includes a convex shape with respect to the bottom surface of the insulating layer.

11. The circuit substrate of claim 3 ,
wherein the curved surface includes a concave shape with respect to the bottom surface of the insulating layer.

12. The circuit substrate of claim 2 ,
wherein the second portion is extended to the insulating layer from the connection portion.

13. The circuit substrate of claim 1 ,
wherein a lower conductive layer is disposed on the bottom surface of the insulating layer,
wherein the lower conductive layer includes a top surface facing the insulating layer and a bottom surface opposite to the top surface of the lower conductive layer,
wherein a second insulating layer is disposed on the bottom surface of the lower conductive layer,
wherein a portion of the bottom surface of the lower conductive layer is embedded in the second insulating layer.

14. The circuit substrate of claim 13 ,
wherein the curved surface of the cover metal vertically overlaps the lower conductive layer disposed on the bottom surface of the insulating layer.

15. A semiconductor package comprising:
an insulating layer including a top surface and a bottom surface opposite to the top surface;
a circuit layer disposed on the insulating layer;
a cover metal layer disposed on the circuit layer; and
a semiconductor chip electrically connected to the cover metal layer,
wherein the circuit layer includes a portion that is positioned higher than or equal to the top surface of the insulating layer with respect to the bottom surface of the insulating layer,
wherein the cover metal layer includes a cover portion that is positioned higher than the top surface of the insulating layer,
wherein the cover portion of the cover metal layer includes a first portion that is vertically overlapped with the portion of the circuit layer, and a second portion that is not vertically overlapped with the portion of the circuit metal layer,
wherein a bottom surface of the first portion of the cover portion is in contact with the portion of the circuit layer,
wherein a top surface of the second portion includes a curved surface, and
wherein the second portion of the cover portion of the cover metal layer is horizontally overlapped with the circuit layer.

16. The semiconductor package of claim 15 ,
wherein the cover portion of the cover metal layer includes a connection portion disposed between the first portion of the cover portion of the cover metal layer and the second portion of the cover portion of the cover metal layer, and
wherein the connection portion is in contact with the circuit layer.

17. The semiconductor package of claim 16 ,
wherein the second portion is extended outward from the connecting portion,
wherein the curved surface is bent toward the insulating layer.

18. The semiconductor package of claim 15 ,
wherein a lower conductive layer is disposed on the bottom surface of the insulating layer,
wherein the lower conductive layer includes a top surface facing the insulating layer and a bottom surface opposite to the top surface of the lower conductive layer,
wherein a second insulating layer is disposed on the bottom surface of the lower conductive layer,
wherein a portion of the bottom surface of the lower conductive layer is embedded in the second insulating layer.

19. The semiconductor package of claim 18 ,
wherein the curved surface of the cover metal vertically overlaps the lower conductive layer disposed on the bottom surface of the insulating layer.

20. The semiconductor package of claim 15 ,
wherein a first height between a top surface of the portion of the circuit layer and the top surface of the insulating layer is greater than a second height between a bottom surface of the second portion and the top surface of the insulating layer.

Assignees

• Lg Innotek Co Ltd

Inventors

• Cho Sung Oh
• Kim Yoon Tai

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W74/00

  Encapsulations, e.g. protective coatings · CPC title

• H10W90/701 Primary

  characterised by the relative positions of pads or connectors relative to package parts · CPC title

• H10W70/685

  comprising multiple insulating layers · CPC title

• H10W70/66

  Conductive materials thereof · CPC title