Shift register, gate driving circuit and display panel

Patent metadata

Field	Value
Publication number	US-11875715-B2
Application number	US-202017417470-A
Country	US
Kind code	B2
Filing date	Dec 29, 2020
Priority date	Feb 25, 2020
Publication date	Jan 16, 2024
Grant date	Jan 16, 2024

Abstract

The disclosure provides a shift register, a gate driving circuit and a display panel. The shift register includes: an input sub-circuit and a first output sub-circuit; the input sub-circuit pre-charges, in response to an input signal, a pull-up node by a first power voltage; the pull-up node is a coupling node at which the input sub-circuit and the output sub-circuit are coupled; the first output sub-circuit outputs a clock signal through a first signal output terminal in response to a potential of the pull-up node; the shift register further includes: a first noise reduction sub-circuit and/or a second noise reduction sub-circuit; the first noise reduction sub-circuit performs noise reduction on the pull-up node through a non-operation level signal in a blank period; the second noise reduction sub-circuit performs noise reduction on the first signal output terminal by the non-operation level signal during the blank period.

First claim

The invention claimed is:

1. A shift register, comprising: an input sub-circuit and a first output sub-circuit;
the input sub-circuit is configured to pre-charge, in response to an input signal, a pull-up node by a first power voltage; the pull-up node is a coupling node at which the input sub-circuit and the first output sub-circuit are coupled;
the first output sub-circuit is configured to output a clock signal through a first signal output terminal in response to a potential of the pull-up node; wherein,
the shift register further comprises a first noise reduction sub-circuit and/or a second noise reduction sub-circuit;
the first noise reduction sub-circuit is configured to perform, in response to a first noise reduction control signal, noise reduction on the pull-up node through a non-operation level signal in a blank period;
the second noise reduction sub-circuit is configured to perform, in response to a second noise reduction control signal, noise reduction on the first signal output terminal by a non-operation level signal during the blank period,
the shift register further comprising: a plurality of second output sub-circuits; each of the plurality of second output sub-circuits is configured to output a signal output from the first signal output terminal through a second signal output terminal corresponding thereto in response to a switch control signal corresponding thereto;
the shift register further comprising: a pull-down control sub-circuit, a pull-down sub-circuit, a third noise reduction sub-circuit, a fourth noise reduction sub-circuit;
the pull-down control sub-circuit is configured to transmit, in response to an operation level signal, the operation level signal to a pull-down node; the pull-down node is a coupling node at which the pull-down control sub-circuit and the pull-down sub-circuit are coupled;
the pull-down sub-circuit is configured to pull down a potential of the pull-down node by the non-operation level signal in response to the potential of the pull-up node;
the third noise reduction sub-circuit is configured to perform noise reduction on the pull-up node by the non-operation level signal in response to the potential of the pull-down node;
the fourth noise reduction sub-circuit is configured to perform noise reduction on the first signal output terminal by the non-operation level signal in response to the potential of the pull-down node; and wherein
the shift register further comprising a plurality of fifth noise reduction sub-circuits provided in one-to-one correspondence with the plurality of second signal output terminals;
each of the plurality of fifth noise reduction sub-circuits is configured to perform, in response to the potential of the pull-down node, noise reduction on the second output terminal corresponding thereto by the non-operation level signal in the blank period.

2. The shift register of claim 1 , wherein the first noise reduction sub-circuit comprises a first transistor;
a first electrode of the first transistor is coupled with the pull-up node, a second electrode of the first transistor is coupled with a non-operation level terminal, and a control electrode of the first transistor is coupled with a first noise reduction control signal terminal.

3. The shift register of claim 1 , wherein the second noise reduction sub-circuit comprises a second transistor;
a first electrode of the second transistor is coupled with the first signal output terminal, a second electrode of the second transistor is coupled with the non-operation level terminal, and a control electrode of the second transistor is coupled with a second noise reduction control signal terminal.

4. The shift register of claim 1 , wherein each of the plurality of second output sub-circuits comprises a third transistor;
a first electrode of the third transistor is coupled with the first signal output terminal, a second electrode of the third transistor is coupled with the second signal output terminal, and a control electrode of the third transistor is coupled with a switch control signal terminal.

5. The shift register of claim 1 , wherein each of the plurality of second output sub-circuits comprises a third transistor;
a first electrode of the third transistor is coupled with a driving signal terminal corresponding to the third transistor, a second electrode of the third transistor is coupled with the second signal output terminal, and a control electrode of the third transistor is coupled with the first signal output terminal.

6. The shift register of claim 1 , wherein the pull-down control sub-circuit comprises a fourth transistor and a fifth transistor;
a first electrode of the fourth transistor is coupled with a control electrode of the fourth transistor, a first electrode of the fifth transistor and an operation level terminal, and a second electrode of the fourth transistor is coupled with the pull-down sub-circuit and a control electrode of the fifth transistor; and a second electrode of the fifth transistor is coupled to the pull-down node.

7. The shift register of claim 1 , wherein the pull-down sub-circuit comprises a sixth transistor and a seventh transistor;
a first electrode of the sixth transistor is coupled with the pull-down node, a second electrode of the sixth transistor is coupled with the non-operation level terminal, and a control electrode of the sixth transistor is coupled with the pull-up node;
a first electrode of the seventh transistor is coupled with a pull-down control sub-circuit, a second electrode of the seventh transistor is coupled with the non-operation level terminal, and a control electrode of the seventh transistor is coupled with the pull-up node.

8. The shift register of claim 1 , wherein the third noise reduction sub-circuit comprises an eighth transistor;
a first electrode of the eighth transistor is coupled with the pull-up node, a second electrode of the eighth transistor is coupled with the non-operation level terminal, and a control electrode of the eighth transistor is coupled with the pull-down node.

9. The shift register of claim 1 , wherein the fourth noise reduction sub-circuit comprises a ninth transistor;
a first electrode of the ninth transistor is coupled with the first signal output terminal, a second electrode of the ninth transistor is coupled with the non-operation level terminal, and a control electrode of the ninth transistor is coupled with the pull-down node.

10. The shift register of claim 1 , wherein each of the plurality of fifth noise reduction sub-circuits comprises a tenth transistor;
a first electrode of the tenth transistor is coupled with the second signal output terminal corresponding to the tenth transistor, a second electrode of the tenth transistor is coupled with the non-operation level terminal, and a control electrode of the tenth transistor is coupled with the pull-down node.

11. The shift register of claim 1 , further comprising a reset sub-circuit;
the reset sub-circuit is configured to reset the pull-up node by a second power voltage in response to a reset signal.

12. The shift register of claim 11 , wherein the reset sub-circuit comprises an eleventh transistor;
a first electrode of the eleventh transistor is coupled with the pull-up node, a second electrode of the eleventh transistor is coupled with a second power voltage terminal, and a control electrode of the eleventh transistor is coupled with a reset signal terminal.

13. The shift register of claim 1 , wherein the input sub-circuit comprises a twelfth transistor;
a first electrode of the twelfth transistor is coupled with a first power voltage terminal, a second electrode of the

Assignees

• Hefei Boe Optoelectronics Tech
• Boe Technology Group Co Ltd

Inventors

• Gu Honggang
• Chen Junsheng
• Song Jie

Classifications

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G11C19/28 Primary

  using semiconductor elements (G11C19/14, G11C19/36 take precedence) · CPC title

• G09G2300/0408

  Integration of the drivers onto the display substrate · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title