Platform controller hub (PCH) chipsets in platforms as extended IO expander(s)

Patent metadata

Field	Value
Publication number	US-11874787-B2
Application number	US-202016790648-A
Country	US
Kind code	B2
Filing date	Feb 13, 2020
Priority date	Feb 13, 2020
Publication date	Jan 16, 2024
Grant date	Jan 16, 2024

Abstract

Methods to dynamically configure, monitor and govern PCH Chipsets in platforms as extended IO-expander(s) and associated apparatus. A multi-role PCH is provided that may be dynamically configured as a legacy PCH to facilitate booting for platforms without bootable CPUs and as IO-expanders in single-socket and multi-socket platforms. A control entity is coupled to the PCHs and is used to effect boot, reset, wake, and power management operations by exchanging handshake singles with the PCHs and providing control inputs to CPUs on the platforms. The single-socket platform configurations include a platform with a CPU with bootable logic coupled to an IO-expander and a platform with a legacy CPU coupled to a legacy PCH. The multi-socket platforms include a platform with a bootable CPU coupled to one or more non-legacy CPUs and employing multiple IO-expanders and platform with a legacy CPU coupled to one or more non-legacy CPUs and coupled to a legacy PCH, and further including one or more PCHs coupled to the non-legacy CPU(s) implemented as IO-expanders.

First claim

What is claimed is:

1. A method implemented on a platform including one or more central processing units (CPUs), a firmware storage device in which platform firmware is stored, and one or more controller hubs coupled to a platform control entity, each controller hub including a plurality of Input-Output (TO) interfaces and coupled to a respective CPU, each controller hub including at least one pin strap used to configure the controller hub to be implemented as a legacy controller hub or an IO-expander, the method comprising:
configurating at least one controller hub to be implemented as an IO expander under which the controller hub is used to expand the IO interfaces available to the CPU to which the controller hub is coupled; and
detecting a logic level at the at least one pin strap, and, in response thereto configuring the controller hub to be implemented as a legacy controller hub or an IO-expander.

2. The method of claim 1 , wherein one of the one or more CPUs is a legacy CPU coupled to a legacy controller hub, further comprising:
booting the platform by sending at least a portion of the platform firmware to the legacy CPU via the legacy controller hub.

3. The method of claim 2 , wherein the platform includes one or more controller hubs separate from the legacy controller hub, further comprising:
configuring the one or more controller hubs separate from the legacy controller hub as IO expanders;
in connection with booting the platform or waking the platform from a sleep state,
triggering, via the legacy controller hub, the platform to assert a wake up for each IO-expander;
sending a wake signal from the platform control entity to each IO-expander; and
for each IO-expander, in response to receiving a wake signal, initiating booting of the IO-expander.

4. The method of claim 3 , further comprising:
for each IO-expander,
when the IO-expander completes booting, returning an acknowledgement (ACK) signal to the platform control entity to indicate the IO-expander has booted;

verifying, via the platform control entity that each IO-expander has booted;
sending an aggregated ACK to the legacy controller hub indicating each IO-expander has booted; and
generating, via the legacy controller hub, a reset of the one or more CPUs.

5. The method of claim 1 , wherein the compute platform includes a plurality of controller hubs and the plurality of CPUs include a CPU with bootable logic that is coupled to the firmware storage device and coupled to a first controller hub, further comprising:
configuring each of the plurality of controller hubs including the first controller hub to operate as an IO-expander;
booting the platform by accessing the platform firmware stored in the firmware storage device via the CPU with bootable logic;
booting the first controller hub; and
coordinating booting of each of the IO-expanders other than the first controller hub via handshake signals sent between the first controller hub and the platform control entity and handshake signals sent between the platform control entity and each of those IO-expanders.

6. The method of claim 5 , wherein each of the plurality of controller hubs include a plurality of IO pins coupled to a set of handshake wires, further comprising:
sending a platform reset handshake signal from a first IO pin of the first controller hub to the platform control entity;
for each controller hub other than the first controller hub,
receiving a wake handshake signal from the platform control entity at a second IO pin;
booting or waking the controller hub; and
when the controller hub has successfully booted or has awaken, sending a wake acknowledgement (ACK) signal from a third IO pin on the controller hub to the platform control entity;

verifying, via the platform control entity, that a wake ACK signal has been received from each controller hub other than the first controller hub; and
triggering a reset for each of the plurality of CPUs.

7. The method of claim 1 , further comprising:
detecting the platform has triggered entry from a normal operating state to a sleep state;
triggering entry of each IO expander to enter the sleep state;
for each IO expander,
entering the sleep state; and
returning an acknowledgement (ACK) handshake signal to the platform control entity indicating the IO-expander has entered the sleep state.

8. The method of claim 7 , wherein each controller hub includes one or more General Purpose IO (GPIO) pins coupled to a respective handshake line coupled between the controller hub and the platform control entity, and wherein an IO-expander is triggered to enter a sleep state by setting a voltage level of handshake signals output by the platform control entity that are coupled to GPIO input pins on each controller hub to a predefined logic level.

9. The method of claim 1 , wherein the platform control entity comprises one of:
a discrete device comprising a complex programmable logic device (CLPD);
a discrete device comprising a field programmable gate array (FPGA);
a discrete device comprising an embedded controller;
a logic block in one of the plurality of CPUs; or
a discrete device in a multi-chip package including one of the plurality of CPUs.

10. A compute platform comprising:
a plurality of central processing units (CPUs), each CPU associated with a respective socket and connected to at least one other CPU via a socket-to-socket interconnect;
a firmware storage device in which platform firmware is stored;
one or more controller hubs, each controller hub connected to a respective CPU and having a plurality of Input-Output (TO) interfaces, at least one controller hub configured to be implemented as an IO-expander under which the controller hub is used to expand the IO interfaces available to a CPU to which the controller hub is coupled; and
a platform control entity, coupled to each controller hub via a respective set of handshake wires,
wherein the platform is configured to control booting of each of the at least one controller hubs configured to be implemented as an IO-expander using handshake signals exchanged over the set of handshake wires coupling that controller hub to the platform control entity, wherein one of the plurality of CPUs is a legacy CPU that is not capable of booting on its own that is coupled to a first controller hub that is coupled to the firmware storage device, wherein the first controller hub is implemented as a legacy controller hub, wherein the platform is booted by accessing the platform firmware stored in the firmware storage device via the legacy controller hub and sending at least a portion of the platform firmware that is accessed to the legacy CPU.

11. The compute platform of claim 10 , further configured to:
in connection with booting the platform or waking the platform from a sleep state,
trigger, via the legacy controller hub, the platform to assert a wake up for each IO-expander;
send a wake signal from the platform control entity to each IO-expander; and
for each IO-expander, in response to receiving a wake signal, initiating booting or waking of the IO-expander.

12. The compute platform of claim 11 , further configured to:
for each IO-expander,
when the IO-expander completes booting or waking, return an acknowledgement (ACK) signal to the platform control entity to indicate the IO-expander has booted or awaken;

verify, via the platform control entity that each IO-expander has booted or awaken;
send an aggregated ACK to the legacy controller hub indicating each IO-expander has booted or awaken; and
generate, via the legacy controller hub, a reset of the CPUs connected to the IO-expanders.

13.

Assignees

• Intel Corp

Inventors

• Srivastava Amit K
• Shushtarian Majid
• Enamandram Anand K
• Havican Jared W
• Pihlman Jeffrey A
• Karas Michael J
• Krithivas Ramamurthy
• Watnik Christine

Classifications

• G06F13/4063 Primary

  Device-to-bus coupling · CPC title

• G06F9/4403

  Processor initialisation · CPC title

• G06F9/4418

  Suspend and resume; Hibernate and awake · CPC title

• G06F13/122 Primary

  where hardware performs an I/O function other than control of data transfer · CPC title

• G06F9/4401

  Bootstrapping (security arrangements therefor G06F21/57) · CPC title