Event-based computational pixel imagers
US-2022166948-A1 · May 26, 2022 · US
US11871122B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11871122-B2 |
| Application number | US-202017425809-A |
| Country | US |
| Kind code | B2 |
| Filing date | Feb 4, 2020 |
| Priority date | Feb 4, 2019 |
| Publication date | Jan 9, 2024 |
| Grant date | Jan 9, 2024 |
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A computational pixel imaging device can include multiple counters per pixel that can be used to acquire in-pixel histogram data representative of a signal detected by a pixels detector. Multiple pixel counters can also be used to execute simultaneous signal-processing threads on acquired image data. The imaging device can also include infinite dynamic range sensing and perform signal down-sampling.
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What is claimed is: 1. A pixel integrated circuit in an array of pixel integrated circuits, the pixel integrated circuit comprising: a signal converter, wherein the signal converter is arranged to receive a signal from a detector; a multiplexer connected to an output of the signal converter; two or more counters connected to outputs of the multiplexer; and a sequencer connected to a control input of the multiplexer, wherein the sequencer comprises a counter that issues count values to the multiplexer. 2. The pixel integrated circuit of claim 1 , wherein the sequencer sends digital signals to the multiplexer to select a first of the two or more counters to connect to the output of the signal converter for a first period of time and to select a second of the two or more counters to connect to the output of the signal converter for a second period of time. 3. The pixel integrated circuit of claim 1 , wherein the signal converter is a current-to-frequency signal converter. 4. The pixel integrated circuit of claim 1 , wherein the signal converter is a photon-to-pulse signal converter. 5. The pixel integrated circuit of claim 1 , wherein a first counter of the two or more counters comprises a plurality of flip-flops. 6. The pixel integrated circuit of claim 5 , wherein an output of a flip-flop corresponding to the most significant bit for the first counter connects to a tri-state buffer. 7. The pixel integrated circuit of claim 6 , further comprising: data input multiplexers connected to a data inputs of the plurality of flip-flops; and clock input multiplexers connected to the clock inputs of the plurality of flip-flops. 8. The pixel integrated circuit of claim 5 , wherein the first counter can be configured as a counter and as a shift register. 9. The pixel integrated circuit of claim 1 , wherein a counter of the two or more counters comprises: a b-bit counter; a data line arranged to transmit a value of a most significant bit of the b-bit counter; and read-out circuitry configured to read the most significant bit at a higher read-out rate than a read-out rate for other bits of the b-bit counter. 10. The pixel integrated circuit of claim 1 , wherein the array is located adjacent to an imaging plane of an optical assembly. 11. A method of acquiring in-pixel histograms, the method comprising: converting, with a signal converter located in a pixel integrated circuit of an array of pixel integrated circuits, an analog signal received from a detector to an output signal; and directing the output signal to different counters included in the pixel integrated circuit in a sequence of different times during an exposure period for the detector, wherein the directing is performed, at least in part, with a multiplexer, wherein the directing further comprises providing a sequence of commands, with a sequencer, to the multiplexer that connects an output from the signal converter to a first counter of the different counters for a first period of time and connects an output from the signal converter to a second counter of the different counters for a second period of time. 12. The method of claim 11 , wherein the converting comprises current-to-frequency conversion. 13. The method of claim 11 , wherein the converting comprises photon-to-pulse conversion. 14. The method of claim 11 , wherein the first period had a duration that is different from the second period. 15. The method of claim 11 , further comprising determining a number of photons detected by at least one of the different counters. 16. The method of claim 11 , further comprising determining a time of arrival of an optical pulse based on count values from two or more of the different counters. 17. A computational pixel imager having an array of pixels, one or more of the pixels comprising: a detector; a signal converter connected to receive a signal from the detector; a multiplexer connected to an output of the signal converter; and two or more counters connected to outputs of the multiplexer, wherein a counter of the two or more counters comprises: a b-bit counter; a data line arranged to transmit a value of a most significant bit of the b-bit counter; and read-out circuitry configured to read the most significant bit at a higher read-out rate than a read-out rate for other bits of the b-bit counter. 18. The computational pixel imager of claim 17 , further comprising a sequencer connected to a control input of the multiplexer. 19. The computational pixel imager of claim 17 , wherein the signal converter is a current-to-frequency signal converter. 20. The computational pixel imager of claim 17 , wherein the signal converter is a photon-to-pulse signal converter. 21. The computational pixel imager of claim 17 , wherein a first counter of the two or more counters comprises a plurality of flip-flops. 22. The computational pixel imager of claim 21 , wherein the first counter can be configured as a counter and as a shift register during operation of the computational pixel imager. 23. The computational pixel imager of claim 17 included in a camera.
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