Fault tolerant and error correction decoding method and apparatus for quantum circuit, and chip

Patent metadata

Field	Value
Publication number	US-11870462-B2
Application number	US-202117463090-A
Country	US
Kind code	B2
Filing date	Aug 31, 2021
Priority date	Apr 15, 2020
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

This disclosure discloses a fault tolerant and error correction decoding method and apparatus for a quantum circuit, and a chip. This disclosure relates to the field of artificial intelligence (AI) and quantum technologies. The method includes: obtaining actual error syndrome information of a quantum circuit by performing a noisy error syndrome measurement on the quantum circuit by using a quantum error correction (QEC) code; decoding the actual error syndrome information to obtain a logic error class and perfect error syndrome information that correspond to the actual error syndrome information; and determining error result information of the quantum circuit based on the logic error class and the perfect error syndrome information, the error result information being indicative of a data qubit in which an error occurs in the quantum circuit and a corresponding error class.

First claim

What is claimed is:

1. A fault tolerant and error correction decoding method for a quantum circuit, applicable to a computer device, the method comprising:
obtaining actual error syndrome information of a quantum circuit by performing a noisy error syndrome measurement on the quantum circuit using a quantum error correction (QEC) code;
decoding the actual error syndrome information to obtain a logic error class and perfect error syndrome information, which correspond to the actual error syndrome information, the logic error class being a class obtained through mapping of an error occurring in the quantum circuit and the perfect error syndrome information being obtained by performing a noise-free error syndrome measurement on the quantum circuit; and
determining error result information of the quantum circuit based on the logic error class and the perfect error syndrome information, the error result information being indicative of a data qubit in which an error occurs in the quantum circuit and a corresponding error class.

2. The method according to claim 1 , wherein decoding the actual error syndrome information to obtain a logic error class and perfect error syndrome information comprises:
decoding the actual error syndrome information using a first decoder to obtain the logic error class corresponding to the actual error syndrome information, the first decoder being a neural network classifier configured to determine the logic error class; and
decoding the actual error syndrome information using one or more second decoders to obtain the perfect error syndrome information corresponding to the actual error syndrome information, the one or more second decoders being a neural network classifier configured to determine the perfect error syndrome information.

3. The method according to claim 2 , wherein decoding the actual error syndrome information using the first decoder to obtain the logic error comprises:
partitioning the actual error syndrome information using the first decoder to obtain at least two blocks;
performing feature extraction on the at least two blocks in parallel to obtain feature information; and
performing fusion decoding on the feature information by using the first decoder to obtain the logic error class.

4. The method according to claim 2 , wherein decoding the actual error syndrome information using the one or more second decoders to obtain the perfect error syndrome information comprises:
respectively inputting the actual error syndrome information into k second decoders to obtain k perfect error syndrome bits, k being a positive integer and k being related to a scale of the QEC code; and
integrating the k perfect error syndrome bits to obtain the perfect error syndrome information corresponding to the actual error syndrome information.

5. The method according to claim 2 , further comprising training the first decoder and the one or more second decoders by:
simulating a data error and a measurement error of a sample quantum circuit to obtain a simulation result, the data error occurring on a data qubit of the sample quantum circuit and the measurement error occurring during an error syndrome measurement;
obtaining, based on the simulation result, T pieces of error syndrome information of the sample quantum circuit from T error syndrome measurements, T being an integer greater than 1;
determining equivalent data error information obtained by projecting the T pieces of error syndrome information to a target time point;
determining a logic error class and perfect error syndrome information that correspond to the equivalent data error information;
constructing a training sample, sample data of the training sample comprising the T pieces of error syndrome information, the training sample comprising label data, the label data comprising the logic error class and the perfect error syndrome information that correspond to the equivalent data error information; and
training the first decoder and the one or more second decoders by using the training sample.

6. The method according to claim 5 , wherein simulating the data error and the measurement error of the sample quantum circuit comprises:
probabilistically generating an error on a data qubit comprised in the sample quantum circuit;
probabilistically generating an error on an auxiliary qubit corresponding to the sample quantum circuit, the auxiliary qubit being configured to measure the error syndrome information of the sample quantum circuit;
probabilistically generating an error on a controlled-not (CNOT) gate comprised in an eigenvalue measurement circuit, the eigenvalue measurement circuit being corresponding to the sample quantum circuit and being configured to measure an eigenvalue of a stabilizer generator; and
probabilistically generating a measurement error when an error syndrome measurement is performed on the sample quantum circuit by using the QEC code.

7. The method according to claim 5 , wherein simulating the data error and the measurement error of the sample quantum circuit comprises:
performing quantum process tomography (QPT) on the sample quantum circuit to extract a noise model of the sample quantum circuit, the noise model being configured to generate the data error and the measurement error through simulation; and
simulating an evolution of a quantum state of the sample quantum circuit under the action of noise based on the noise model.

8. The method according to claim 2 , further comprising training the first decoder and the one or more second decoders by:
performing a noisy error syndrome measurement on the sample quantum circuit to obtain error syndrome information of the sample quantum circuit;
decoding the error syndrome information of the sample quantum circuit by using another decoder to obtain a logic error class and perfect error syndrome information, which correspond to the error syndrome information of the sample quantum circuit;
constructing a training sample, sample data of the training sample comprising the error syndrome information of the sample quantum circuit, the training sample comprising label data, and the label data comprising the logic error class and the perfect error syndrome information; and
training the first decoder and the one or more second decoders by using the training sample.

9. The method according to claim 1 , wherein determining the error result information of the quantum circuit based on the logic error class and the perfect error syndrome information comprises:
obtaining a first error result corresponding to the logic error class;
obtaining a second error result corresponding to the perfect error syndrome information; and
determining the error result information of the quantum circuit based on the first error result and the second error result.

10. The method according to claim 9 , wherein obtaining the first error result corresponding to the logic error class comprises:
selecting any element from elements comprised in the logic error class as the first error result,
the logic error class comprising at least one equivalent error element.

11. The method according to claim 9 , wherein obtaining the second error result corresponding to the perfect error syndrome information comprises:
searching a mapping table for simple errors respectively corresponding to error syndrome points in the perfect error syndrome information, the mapping table comprising at least one set of mapping relationship between an error syndrome point and a simple error; and
multiplying the simple errors respectively corresponding to the error syndrome points to obtain the second error result.

12. The method according to claim 9 , wherein dete

Assignees

• Tencent Tech Shenzhen Co Ltd

Inventors

• Zheng Yicong
• Zhang Shengyu

Classifications

• G06N3/09

  Supervised learning · CPC title

• G06N3/0464

  Convolutional networks [CNN, ConvNet] · CPC title

• G06N10/20

  Models of quantum computing, e.g. quantum circuits or universal quantum computers · CPC title

• G06N10/70

  Quantum error correction, detection or prevention, e.g. surface codes or magic state distillation · CPC title

• H03M13/1575 Primary

  Direct decoding, e.g. by a direct determination of the error locator polynomial from syndromes and subsequent analysis or by matrix operations involving syndromes, e.g. for codes with a small minimum Hamming distance · CPC title