Voltage regulation

Patent metadata

Field	Value
Publication number	US-11869603-B2
Application number	US-202117401524-A
Country	US
Kind code	B2
Filing date	Aug 13, 2021
Priority date	Aug 13, 2021
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

Integrated circuit devices might include a voltage regulator comprising an input and an output, a selectively activated current path connected between the input and output, and a controller configured to cause the integrated circuit device to connect the output to the input through the current path when a voltage level of the input has a first voltage level, maintain the connection of the output and the input through the current path until the voltage level of the input has a second voltage level higher than the first voltage level, isolate the output from the input through the current path after the voltage level of the input has the second voltage level, and regulate a voltage level of the output while the output is isolated from the input through the current path.

First claim

What is claimed is:

1. A voltage regulation system, comprising:
a voltage regulator comprising an input, an output and a selectively activated first current path between its input and its output; and
a voltage tracker comprising a first input connected to the input of the voltage regulator, a second input configured to receive a control signal, an output connected to the output of the voltage regulator, and a selectively activated second current path connected between the input of the voltage regulator and the output of the voltage regulator;
wherein the voltage tracker is configured to enable the second current path for activation in response to a voltage level of the input of the voltage regulator in response to the control signal having a first logic level; and
wherein the voltage tracker is configured to disable the second current path from activation in response to the voltage level of the input of the voltage regulator in response to the control signal having a second logic level different than the first logic level.

2. The voltage regulation system of claim 1 , wherein the second current path comprises an n-type field-effect transistor (nFET) comprising a control gate capacitively coupled to the input of the voltage regulator, a first source/drain connected to the input of the voltage regulator, and a second source/drain connected to the output of the voltage regulator.

3. The voltage regulation system of claim 2 , wherein the nFET has a negative threshold voltage.

4. The voltage regulation system of claim 1 , wherein the voltage tracker further has a selectively activated third current path connected between the input of the voltage regulator and the output of the voltage regulator.

5. The voltage regulation system of claim 4 , wherein the voltage tracker is configured to enable the third current path for activation in response to a voltage level of the input of the voltage regulator in response to the control signal having the first logic level, and wherein the voltage tracker is configured to disable the third current path from activation in response to the voltage level of the input of the voltage regulator in response to the control signal having the second logic level.

6. The voltage regulation system of claim 4 , wherein the third current path comprises a p-type field-effect transistor (pFET) comprising a first source/drain connected to the input of the voltage regulator, and a second source/drain connected to the output of the voltage regulator.

7. The voltage regulation system of claim 6 , wherein the second current path comprises an n-type field-effect transistor (nFET) comprising a control gate capacitively coupled to the input of the voltage regulator, a first source/drain connected to the input of the voltage regulator, and a second source/drain connected to the output of the voltage regulator.

8. The voltage regulation system of claim 7 , wherein the pFET is a first pFET and the nFET is a first nFET, and wherein the voltage tracker further comprises:
a first capacitor comprising a first electrode connected to the input of the voltage regulator, and a second electrode connected to the control gate of the first nFET;
a second pFET comprising a control gate, a first source/drain connected to the input of the voltage regulator, and a second source/drain connected to the control gate of the first nFET;
a second nFET comprising a control gate, a first source/drain connected to the control gate of the first nFET, and a second source/drain connected to a voltage node;
a third pFET comprising a control gate connected to the second source/drain of the second pFET, a first source/drain connected to the input of the voltage regulator, and a second source/drain connected to the control gate of the second pFET;
a third nFET comprising a control gate, a first source/drain connected to the second source/drain of the third pFET, and a second source/drain connected to the voltage node;
a first inverter comprising an input connected to the second input of the voltage tracker, and an output connected to the control gate of the third nFET;
a second inverter comprising an input connected to the output of the first inverter, and an output connected to the control gate of the second nFET; and
a second capacitor comprising a first electrode connected to the input of the voltage regulator, and a second electrode connected to the output of the first inverter.

9. A memory, comprising:
a voltage regulator comprising an input and an output;
a selectively activated first current path connected between the input of the voltage regulator and the output of the voltage regulator;
a selectively activated second current path connected between the input of the voltage regulator and the output of the voltage regulator;
an array of memory cells connected to the output of the voltage regulator; and
a controller connected to the output of the voltage regulator, wherein the controller is configured to cause the memory to:
connect the output of the voltage regulator to the input of the voltage regulator through the first current path in response to a voltage level of the input of the voltage regulator having a first voltage level;
connect the output of the voltage regulator to the input of the voltage regulator through the second current path in response to the voltage level of the input of the voltage regulator having a second voltage level higher than the first voltage level;
maintain the connection of the output of the voltage regulator to the input of the voltage regulator through the first current path until the voltage level of the input of the voltage regulator has a third voltage level higher than the second voltage level;
maintain the connection of the output of the voltage regulator to the input of the voltage regulator through the second current path until the voltage level of the input of the voltage regulator has the third voltage level;
isolate the output of the voltage regulator from the input of the voltage regulator through the first current path and through the second current path after the voltage level of the input of the voltage regulator has the third voltage level; and
regulate a voltage level of the output of the voltage regulator while the output of the voltage regulator is isolated from the input of the voltage regulator through the first current path and through the second current path.

10. The memory of claim 9 , wherein the first current path comprises an n-type field-effect transistor (nFET) comprising a control gate capacitively coupled to the input of the voltage regulator, a first source/drain connected to the input of the voltage regulator, and a second source/drain connected to the output of the voltage regulator.

11. The memory of claim 10 , wherein the nFET has a negative threshold voltage.

12. The memory of claim 10 , wherein the second current path comprises a p-type field-effect transistor (pFET) comprising a first source/drain connected to the input of the voltage regulator, and a second source/drain connected to the output of the voltage regulator.

13. The memory of claim 12 , wherein the pFET is a first pFET and the nFET is a first nFET, and wherein the memory further comprises:
a first capacitor comprising a first electrode connected to the input of the voltage regulator, and a second electrode connected to the control gate of the first nFET;
a second pFET comprising a control gate, a first source/drain connected to the input of the voltage regulator, and a second source/drain connected to the control gate of the first nFET;
a second nFET comprising a control gate, a first source/drain connected to the control gat

Assignees

• Micron Technology Inc

Inventors

• Xu Shuai
• Piccardi Michele
• Lee June

Classifications

• G11C16/30 Primary

  Power supply circuits · CPC title

• G05F1/575 Primary

  characterised by the feedback circuit · CPC title

• G11C16/0483

  comprising cells having several storage transistors connected in series · CPC title