Pixel and display apparatus including the same

Patent metadata

Field	Value
Publication number	US-11869433-B2
Application number	US-202217878905-A
Country	US
Kind code	B2
Filing date	Aug 2, 2022
Priority date	Aug 3, 2021
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

A pixel of a display apparatus includes a light emitting device and a pixel circuit connected to first to third gate control lines and the light emitting device, the pixel circuit including first to fourth nodes. The pixel circuit includes a driving transistor connected to the first to third nodes, a first transistor connected to the first gate control line and the first and second nodes, a second transistor connected to the second gate control line, the second node, and a first driving voltage line, a third transistor connected to the first gate control line, the third node, and the fourth node, a fourth transistor connected to the first gate control line, the fourth node, and an initialization voltage line, a fifth transistor connected to the third gate control line, the third node, and a data line, and a storage capacitor between the first node and the fourth node.

First claim

What is claimed is:

1. A pixel, comprising:
a light emitting device; and
a pixel circuit connected to first to third gate control lines and the light emitting device, the pixel circuit including first to fourth nodes,
wherein the pixel circuit comprises:
a driving transistor connected to the first to third nodes;
a first transistor connected to the first gate control line and the first and second nodes;
a second transistor connected to the second gate control line, the second node, and a first driving voltage line;
a third transistor connected to the first gate control line, the third node, and the fourth node;
a fourth transistor connected to the first gate control line, the fourth node, and an initialization voltage line;
a fifth transistor connected to the third gate control line, the third node, and a data line; and
a storage capacitor between the first node and the fourth node, and

wherein:
the pixel circuit is driven in first to fifth intervals,
a signal of the first gate control line has a first voltage level in the first to third intervals and has a second voltage level differing from the first voltage level in the fourth and fifth intervals,
a signal of the second gate control line has the first voltage level in the second to fourth intervals and has the second voltage level in the first and fifth intervals, and
a signal of the third gate control line has the first voltage level in the first interval and the third to fifth intervals and has the second voltage level in the second interval.

2. The pixel of claim 1 , wherein some of the driving transistor and the first to fifth transistors have a first conductive type, and the other transistors have a second conductive type which differs from the first conductive type.

3. The pixel of claim 2 , wherein the driving transistor and the first and fourth transistors have the first conductive type, and
the second, third, and fifth transistors have the second conductive type.

4. The pixel of claim 2 , wherein some of the driving transistor and the first to fifth transistors comprise an oxide semiconductor layer including oxide, and the other transistors comprise a silicon semiconductor layer including crystalline silicon.

5. The pixel of claim 4 , wherein the driving transistor comprises the oxide semiconductor layer having the first conductive type.

6. The pixel of claim 5 , wherein the first and fourth transistors comprise the oxide semiconductor layer having the first conductive type.

7. The pixel of claim 4 , wherein the second, third, and fifth transistors comprise the silicon semiconductor layer having the second conductive type.

8. The pixel of claim 1 , wherein:
the first transistor is turned on in only the first to third intervals among the first to fifth intervals;
the second transistor is turned on in only the first and fifth intervals among the first to fifth intervals;
the third transistor is turned on in only the fourth and fifth intervals among the first to fifth intervals;
the fourth transistor is turned on in only the first to third intervals among the first to fifth intervals; and
the fifth transistor is turned on in only the second interval among the first to fifth intervals.

9. A display apparatus, comprising:
a substrate including a display area, including a plurality of pixels arranged in a first direction and a second direction crossing the first direction, and a non-display area disposed near the display area; and
a gate driver disposed in the non-display area to supply a scan signal, a first emission control signal, and a second emission control signal to each of the plurality of pixels,
wherein two pixels adjacent to each other in the second direction among the plurality of pixels share one or more of the first and second emission control signals,
wherein the pixel circuit of each of the plurality of pixels is driven in first to fifth intervals, and
wherein the pixel circuit of each of the two pixels is identically driven in the first, fourth, and fifth intervals of the first to fifth intervals and is differently driven in the second and third intervals.

10. The display apparatus of claim 9 , wherein:
each of the plurality of pixels comprises a pixel circuit including a light emitting device, a driving transistor, first to fifth transistors, and a storage capacitor; and
some of the driving transistor and the first to fifth transistors have a first conductive type, and the other transistors have a second conductive type which differs from the first conductive type.

11. The display apparatus of claim 10 , wherein some of the driving transistor and the first to fifth transistors comprise an oxide semiconductor layer including oxide, and the other transistors comprise a silicon semiconductor layer including crystalline silicon.

12. The display apparatus of claim 11 , wherein:
the driving transistor among the driving transistor and the first to fifth transistors comprises the oxide semiconductor layer having the first conductive type;
the first and fourth transistors comprise the oxide semiconductor layer or the silicon semiconductor layer having the first conductive type; and
the second, third, and fifth transistors comprise the silicon semiconductor layer having the second conductive type.

13. The display apparatus of claim 9 , wherein the gate driver is configured to:
supply each of the plurality of pixels with the first emission control signal, the second emission control signal, and the scan signal having a first voltage level and a second voltage level which differs from the first voltage level;
supply the first emission control signal and the second emission control signal shared to the two pixels adjacent to each other in the second direction; and
supply different scan signals to the two pixels.

14. The display apparatus of claim 13 , wherein:
the first emission control signal and the second emission control signal overlap partially in an interval having the first voltage level; and
the scan signals supplied to the two pixels do not overlap in an interval having the second voltage level.

15. The display apparatus of claim 9 , wherein:
the second and third intervals of each of the two pixels overlap an interval where the first and second emission control signals have the first voltage level;
the second interval of each of the two pixels is an interval where each scan signal has the second voltage level in an interval where the first and second emission control signals have the first voltage level; and
the third interval of each of the two pixels is an interval other than the second interval in the interval where the first and second emission control signals have the first voltage level.

16. A display apparatus, comprising:
a substrate including a display area, including an n th pixel (where n is an odd number of 1 or more) and an n+1 th pixel vertically adjacent to each other, and first and second non-display areas parallel to each other with the display area therebetween;
a first gate driver supplying a first emission control signal to the n th pixel and the n+1 th pixel in the first non-display area; and
a second gate driver supplying a second emission control signal to the n th pixel and the n+1 th pixel in the second non-display area,
wherein each of the n th pixel and the n+1 th pixel emits light on the basis of the first emission control signal and the second emission control signal,
wherein the pixel circuit of each of the n th pixel and the n+1 th pixel is driven in first to fifth intervals, and
wherein the pixel circuit of each of the

Assignees

• Lg Display Co Ltd

Inventors

• Bong Junho
• Park Minwoo

Classifications

• G09G2330/021

  Power management, e.g. power saving · CPC title

• G09G3/3291

  in which the data driver supplies a variable data voltage for setting the current through, or the voltage across, the light-emitting elements · CPC title

• G09G3/3208

  organic, e.g. using organic light-emitting diodes [OLED] · CPC title

• G09G3/32

  semiconductive, e.g. using light-emitting diodes [LED] · CPC title

• G09G3/2074 Primary

  using sub-pixels · CPC title