Display apparatus and method of driving the same

Patent metadata

Field	Value
Publication number	US-11869400-B2
Application number	US-202117566385-A
Country	US
Kind code	B2
Filing date	Dec 30, 2021
Priority date	Apr 30, 2021
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

A display apparatus is disclosed that comprises a display panel. The display panel includes a display region that includes a first display area and a second display area. A data driver is configured to provide a data voltage to the display region. A gate driver is configured to provide a compensation gate signal and an initialization gate signal to the display region. The gate driver includes a first stage and a second stage. A driving controller is configured to control the gate driver and the data driver. The driving controller is configured to determine a first driving frequency for the first display area and a second driving frequency for the second display area. The second stage is configured to provide the compensation gate signal having a pulse duration shorter than a pulse duration of the compensation gate signal provided to the display region by the first stage.

First claim

What is claimed is:

1. A display apparatus comprising:
a display panel including a display region that includes a first display area and a second display area;
a data driver configured to provide a data voltage to the display region;
a gate driver configured to provide a compensation gate signal and an initialization gate signal to the display region, the gate driver including a first stage and a second stage; and
a driving controller configured to control the gate driver and the data driver,
wherein the driving controller is configured to determine a first driving frequency for the first display area and a second driving frequency for the second display area,
wherein the first and second stages are each configured to receive an input signal having a pulse-on state and a pulse-off state; and
wherein the second stage is configured to provide the compensation gate signal having a pulse duration shorter than a pulse duration of the compensation gate signal provided to the display region by the first stage when the first and second stages both receive the pulse-off state.

2. The display apparatus of claim 1 , wherein the gate driver further comprises a third stage,
wherein the first stage is configured to provide the compensation gate signal synchronized to the first driving frequency and the initialization gate signal synchronized to the first driving frequency to the display region,
wherein the second stage is configured to provide the compensation gate signal synchronized to the first driving frequency and the initialization gate signal synchronized to the second driving frequency to the display region, and
wherein the third stage is configured to provide the compensation gate signal synchronized to the second driving frequency and the initialization gate signal synchronized to the second driving frequency to the display region.

3. The display apparatus of claim 2 , wherein the second stage is disposed between the first stage and the third stage.

4. The display apparatus of claim 2 , wherein the first stage is configured to provide the compensation gate signal and the initialization gate signal to the first display area,
wherein the second stage is configured to provide the compensation gate signal to the first display area and the initialization gate signal to the second display area, and
wherein the third stage is configured to provide the compensation gate signal and the initialization gate signal to the second display area.

5. The display apparatus of claim 1 , wherein the second stage provides the compensation gate signal having the pulse duration equal to the pulse duration of the compensation gate signal provided to the display region by the first stage in a data writing period, and
wherein the second stage provides the compensation gate signal having the pulse duration shorter than the pulse duration of the compensation gate signal provided to the display region by the first stage in a hold period.

6. The display apparatus of claim 1 , wherein a P-th (P is a positive integer) stage of the gate driver is configured to provide the compensation gate signal to a Q-th (Q is a positive integer) pixel row of the display region, and to provide the initialization gate signal to a (Q+N)-th (N is a positive integer) pixel row of the display region, and
wherein a number of the second stages is N.

7. The display apparatus of claim 1 , wherein a pixel of the display region comprises:
a driving transistor configured to generate a driving current;
a switching transistor configured to transmit the data voltage or a blank voltage to a source of the driving transistor in response to a writing gate signal;
a compensation transistor configured to connect the driving transistor in a diode-connection in response to the compensation gate signal;
a storage capacitor configured to store a voltage where a threshold voltage of the driving transistor is subtracted from the data voltage;
a first initialization transistor configured to provide a first initialization voltage to a gate of the driving transistor and the storage capacitor in response to the initialization gate signal;
a first emission transistor configured to connect a line of a pixel power voltage to the source of the driving transistor in response to an emission signal;
a second emission transistor configured to connect a drain of the driving transistor to an emission element in response to the emission signal;
a second initialization transistor configured to provide a second initialization voltage to the emission element in response to the writing gate signal for pixels of a next pixel row; and
the emission element configured to emit light based on the driving current.

8. The display apparatus of claim 1 , wherein each of stages of the gate driver comprises:
an input part configured to transmit the input signal to a first node in response to a first clock signal;
a first stress relieving part disposed between the first node and a second node and configured to transmit a voltage of the first node to the second node;
a first transmitting part configured to transmit a first power voltage to a third node in response to the first clock signal;
a second stress relieving part disposed between the third node and a fourth node and configured to transmit a voltage of the third node to the fourth node;
a first bootstrap part configured to bootstrap the fourth node based on a second clock signal;
a maintaining part configured to maintain a voltage of a fifth node;
a compensation gate signal output part configured to output a second power voltage as the compensation gate signal in response to the voltage of the fifth node;
an initialization gate signal output part configured to output a third power voltage as the initialization gate signal in response to the voltage of the fifth node;
a second bootstrap part configured to bootstrap the second node based on the second clock signal;
a second transmitting part configured to transmit the first clock signal to the third node in response to the voltage of the first node; and
a third transmitting part configured to transmit the second power voltage to the fifth node in response to the voltage of the first node.

9. The display apparatus of claim 8 , wherein the first power voltage is a gate off voltage,
wherein a second power voltage of the first stage and a third power voltage of the first stage are a gate on voltage,
wherein a second power voltage of the second stage is the gate on voltage,
wherein a third power voltage of the second stage is the gate on voltage in a data writing period and is the gate off voltage in a hold period, and
wherein a second power voltage of the third stage and a third power voltage of the third stage are the gate on voltage in the data writing period, and are the gate off voltage in the hold period.

10. The display apparatus of claim 9 , wherein the driving controller is configured to shift the first clock signal and the second clock signal to a time advanced by a compensation time, when the input signal is in a pulse off-state in a period in which the compensation gate signal provided to the display region by the second stage is in a pulse on-state.

11. The display apparatus of claim 10 , wherein the compensation time is determined based on a difference between a voltage value of the compensation gate signal provided to the display region by the first stage during a change from the pulse on-state to the pulse off-state and a voltage value of the compensation gate signal provided to the display region by the second stage during the change from the pulse on-state to the pulse off-state, when the first clock signal equal to the first clock signal

Assignees

• Samsung Display Co Ltd

Inventors

• Kwon Sangan
• Kim Soon-Dong
• Kim Taehoon
• Yun Eun Sil
• Yoon Changnoh

Classifications

• G09G3/20 Primary

  for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix {no fixed position being assigned to or needed to be assigned to the individual characters or partial characters} · CPC title

• G09G2300/0842

  forming a memory circuit, e.g. a dynamic memory with one capacitor · CPC title

• G09G2310/027

  Details of drivers for data electrodes, the drivers handling digital grey scale data, e.g. use of D/A converters · CPC title

• G09G2310/0267

  Details of drivers for scan electrodes, other than drivers for liquid crystal, plasma or OLED displays · CPC title

• G09G2310/08

  Details of timing specific for flat panels, other than clock recovery · CPC title