Non-volatile analog resistive memory cells implementing ferroelectric select transistors
US-11232824-B1 · Jan 25, 2022 · US
US11868868B2 · US · B2
| Field | Value |
|---|---|
| Publication number | US-11868868-B2 |
| Application number | US-202018034287-A |
| Country | US |
| Kind code | B2 |
| Filing date | Nov 27, 2020 |
| Priority date | Nov 6, 2020 |
| Publication date | Jan 9, 2024 |
| Grant date | Jan 9, 2024 |
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Disclosed is a method for implementing an adaptive stochastic spiking neuron based on a ferroelectric field effect transistor, relating to the technical field of spiking neurons in neuromorphic computing. Hardware in the method includes a ferroelectric field effect transistor (fefet), an n-type mosfet, and an l-fefet formed by enhancing a polarization degradation characteristic of a ferroelectric material for the ferroelectric field-effect transistor, wherein a series structure of the fefet and the n-type mosfet adaptively modulates a voltage pulse signal transmitted from a synapse. The l-fefet has a gate terminal connected to a source terminal of the fefet to receive the modulated pulse signal, and simulates integration, leakage, and stochastic spike firing characteristics of a biological neuron, thereby implementing an advanced function of adaptive stochastic spike firing of the neuron.
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What is claimed is: 1. A method for implementing an adaptive stochastic spiking neuron based on a ferroelectric field effect transistor, wherein hardware comprises the ferroelectric field effect transistor (FeFET), an N-type MOSFET, and a Leaky-FeFET (L-FeFET) with an enhanced polarization degradation characteristic, wherein the FeFET has a gate terminal and a drain terminal receiving voltage pulses input from a synapse, respectively, and a source terminal connected to a drain terminal of the N-type MOSFET, wherein a source terminal of the N-type MOSFET is connected to a GND, and a gate terminal of the N-type MOSFET is biased at a fixed voltage lower than a threshold voltage thereof, wherein a series structure of the FeFET and the N-type MOSFET adaptively modulates a voltage pulse signal transmitted from the synapse, and wherein the L-FeFET has a gate terminal connected to the source terminal of the FeFET to receive the modulated pulse signal, a source terminal connected to the GND and a drain terminal serving as an output terminal to generate a current pulse, the L-FeFET being configured to simulate integration, leakage, and spike firing functions of a biological neuron while guaranteeing a function of stochastic spike firing of the neuron by intrinsic stochasticity of ferroelectric polarization reversal, so that the adaptive stochastic spiking neuron is implemented. 2. The method for implementing the adaptive stochastic spiking neuron based on the ferroelectric field effect transistor according to claim 1 , wherein stochasticity of a neuron circuit is regulated by regulating amplitude and width of the input voltage pulse of the neuron circuit. 3. The method for implementing the adaptive stochastic spiking neuron based on the ferroelectric field effect transistor according to claim 1 , wherein the series structure of the FeFET and the N-type MOSFET adaptively regulates the amplitude of the voltage pulse transmitted to L-FeFET as a number of input pulses increases. 4. The method for implementing the adaptive stochastic spiking neuron based on the ferroelectric field effect transistor according to claim 1 , wherein the FeFET and the L-FeFET are ferroelectric field effect transistors based on an MFMIS structure, an MFIS structure, or an MFS structure. 5. The method for implementing the adaptive stochastic spiking neuron based on the ferroelectric field effect transistor according to claim 1 , wherein the FeFET and the L-FeFET are made of a perovskite-type ferroelectric material, a ferroelectric polymer material, or a HfO 2 doped ferroelectric material.
Temporal neural networks, e.g. delay elements, oscillating neurons or pulsed inputs · CPC title
Analogue means · CPC title
using elements simulating biological cells, e.g. neuron · CPC title
using MOS with ferroelectric gate insulating film · CPC title
using electronic means · CPC title
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