High bandwidth core to network-on-chip interface

Patent metadata

Field	Value
Publication number	US-11868296-B2
Application number	US-202217701593-A
Country	US
Kind code	B2
Filing date	Mar 22, 2022
Priority date	Dec 17, 2014
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

An apparatus includes a first port set that includes an input port and an output port. The apparatus further includes a plurality of second port sets. Each of the second port sets includes an input port coupled to the output port of the first port set and an output port coupled to the input port of the first port set. The plurality of second port sets are to each communicate at a first maximum bandwidth and the first port set is to communicate at a second maximum bandwidth that is higher than the first maximum bandwidth.

First claim

What is claimed is:

1. A processor comprising:
a core; and
a router comprising:
a first port set comprising:
an input port to receive first circuit-switched data from the core; and
an output port to provide second circuit-switched data to the core;

a first set of signal lines dedicated to communicate circuit-switched data between a second port set of the router and the output port of the first port set;
a second set of signal lines dedicated to communicate circuit-switched data between a third port set of the router and the output port of the first port set;
a third set of signal lines dedicated to communicate circuit-switched data between the second port set and the input port of the first port set; and
a fourth set of signal lines dedicated to communicate circuit-switched data between the third port set and the input port of the first port set;
wherein the first circuit-switched data comprises first data communicated to the second port set and second data communicated to the third port set, wherein the first data is different from the second data and is communicated simultaneously with the second data.

2. The processor of claim 1 , wherein the input port of the first port set is to simultaneously provide packet-switched data from the core to the second and third port sets.

3. The processor of claim 1 , wherein the output port of the first port set is further to simultaneously provide packet-switched data from the second port set and third port set to the core.

4. The processor of claim 1 , wherein an input port of the second port set is to receive data from a corresponding port of a second router of the processor, and wherein an input port of the third port set is to simultaneously receive data from a corresponding port of a third router of the processor.

5. The processor of claim 1 , wherein an output port of the second port set is to provide data received from the core to a corresponding port of a second router of the processor.

6. The processor of claim 1 , wherein the processor comprises a plurality of routers to communicate with the first router through the second port set and third port set.

7. The processor of claim 6 , wherein a die comprises the processor.

8. The processor of claim 6 , wherein the plurality of routers are to communicate according to a source-synchronous protocol.

9. The processor of claim 6 , wherein the plurality of routers are to communicate according to a synchronous protocol.

10. The processor of claim 1 , wherein the output port of the first port set comprises a first plurality of flip flops sets, each flip flop set of the first plurality of flip flop sets to store packet data provided by a distinct input port of the second port set and third port set, wherein each flip flop set of the first plurality of flip flop sets is to be enabled simultaneously.

11. The processor of claim 1 , wherein an output port of the second port set comprises a plurality of flip flops, each flip flop of the plurality of flip flops to store packet data provided by an input port of the third port set or the input port of the first port set.

12. The processor of claim 1 , wherein:
the input port and the output port of the first port set each comprise an equal number of circuit-switched data carrying wires entering the respective port and exiting the respective port; and
the input port and the output port of the first port set each comprise an equal number of packet-switched data carrying wires entering the respective port and exiting the respective port.

13. The processor of claim 1 , wherein:
the first port set does not arbitrate between data received simultaneously at the output port of the first port set from input ports of the second port set and third port set; and
the first port set does not arbitrate between data sent simultaneously from the input port of the first port set to output ports of the second ports set and third port set.

14. A non-transitory machine readable medium including information to represent structures, when manufactured, comprising:
a core; and
a router comprising:
a first port set comprising:
an input port to receive first circuit-switched data from the core; and
an output port to provide second circuit-switched data to the core;

a first set of signal lines dedicated to communicate circuit-switched data between a second port set and the output port of the first port set; and
a second set of signal lines dedicated to communicate circuit-switched data between a third port set and the output port of the first port set;
a third set of signal lines dedicated to communicate circuit-switched data between the second port set and the input port of the first port set, and
a fourth set of signal lines dedicated to communicate circuit-switched data between the third port set and the input port of the first port set;

wherein the first circuit-switched data comprises first data communicated to the second port set and second data communicated to the third port set, wherein the first data is different from the second data and is communicated simultaneously with the second data.

15. An apparatus comprising:
a core; and
a router comprising:
a first port set comprising:
an input port to receive first circuit-switched data from the core; and
an output port to provide second circuit-switched data to the core;

a second port set comprising an output port to receive a first portion of the first circuit-switched data from the core over a first set of signal lines dedicated to communicate circuit-switched data from the input port of the first port set to the output port of the second port set; and
a third port set comprising an output port to receive a second portion of the first circuit-switched data from the core over a second set of signal lines dedicated to communicate circuit-switched data from the input port of the first port set to the output port of the third port set, wherein the first portion and the second portion of the first circuit-switched data are received simultaneously by the output port of the second port set and the output port of the third port set, and wherein the first portion and second portion of the first circuit-switched data are distinct portions of the first circuit-switched data.

16. The apparatus of claim 15 , wherein the second port set further comprises an input port to provide a first portion of the second circuit-switched data to the output port of the first port set, wherein the third port set further comprises an input port to provide a second portion of the second circuit-switched data to the output port of the first port set, wherein the first portion and the second portion of the second circuit-switched data are provided simultaneously to the output port of the first port set, and wherein the first portion and second portion of the second circuit-switched data are distinct portions of the second circuit-switched data.

17. The processor of claim 1 , and further comprising a network controller, I/O controller hub, audio controller, or wireless transceiver coupled to the processor.

Assignees

• Intel Corp

Inventors

• Kaul Himanshu
• Anders Mark A
• Chen Gregory K

Classifications

• H04L49/10

  characterised by the switching fabric construction · CPC title

• H04L49/112

  Switch control, e.g. arbitration · CPC title

• G06F13/4022 Primary

  using switching circuits, e.g. switching matrix, connection or expansion network (G06F13/4009 takes precedence) · CPC title

• H04L12/54

  Store-and-forward switching systems  (packet switching systems H04L45/00, H04L47/00) · CPC title