Methods and systems for distributing memory requests

Patent metadata

Field	Value
Publication number	US-11868262-B2
Application number	US-202318107962-A
Country	US
Kind code	B2
Filing date	Feb 9, 2023
Priority date	Sep 11, 2018
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

A memory request, including an address, is accessed. The memory request also specifies a type of an operation (e.g., a read or write) associated with an instance (e.g., a block) of data. A group of caches is selected using a bit or bits in the address. A first hash of the address is performed to select a cache in the group. A second hash of the address is performed to select a set of cache lines in the cache. Unless the operation results in a cache miss, the memory request is processed at the selected cache. When there is a cache miss, a third hash of the address is performed to select a memory controller, and a fourth hash of the address is performed to select a bank group and a bank in memory.

First claim

What is claimed is:

1. A method, comprising:
receiving a plurality of memory requests comprising a plurality of addresses, wherein each memory request of the plurality of memory requests comprises a respective address of the plurality of addresses; and
hashing the addresses of the memory requests using a plurality of hashes to distribute the memory requests among a plurality of memory components of a computer system, wherein the plurality of memory components comprises a plurality of caches, a plurality of memory controllers coupled to the plurality of caches, and a plurality of memories coupled to the plurality of memory controllers, and wherein each memory of the plurality of memories comprises a plurality of bank groups;
wherein each hash of the plurality of hashes is respectively programmed to achieve a specific distribution of the plurality of memory requests among the plurality of memory components.

2. The method of claim 1 , wherein the hashes are programmed to achieve an even distribution of the plurality of memory requests across the plurality of memory components so that each cache of the plurality of caches receives a like number of the memory requests.

3. The method of claim 1 , wherein the plurality of hashes comprises a hash that is programmed to select a set of cache lines in a cache of the plurality of caches so that each set of cache lines in the cache receives a like number of the memory requests.

4. The method of claim 1 , wherein the hashes are programmed to achieve an even distribution of the plurality of memory requests across the plurality of memory components so that each memory controller of the plurality of memory controllers receives a like number of the memory requests.

5. The method of claim 1 , wherein the hashes are programmed to achieve an even distribution of the plurality of memory requests across the plurality of memory components so that each bank group of the plurality of bank groups receives a like number of the memory requests.

6. The method of claim 1 , wherein the hashes are programmed to send a number of consecutive memory requests to a same memory controller of the plurality of memory controllers.

7. The method of claim 1 , wherein the hashes are programmed to send memory requests that have addresses within a specified address range to a same memory controller of the plurality of memory controllers.

8. The method of claim 1 , further comprising selecting a group of caches of the plurality of caches by hashing selected bits of a respective address of a memory request of the plurality of memory requests, wherein the selected bits are selected based on a specified distribution of a number of times each group of caches of the plurality of groups of caches is selected.

9. The method of claim 1 , wherein the plurality of hashes comprises:
a hash that is programmed to select a cache of the plurality of caches; and
a hash that is programmed to select a memory controller of the plurality of memory controllers that is closer to the cache than any other memory controller of the plurality of memory controllers.

10. The method of claim 1 , wherein the plurality of hashes comprises a hash that is programmed to select a bank group of the plurality of bank groups and select a bank in the bank group that is selected.

11. A system, comprising:
a first processor;
a plurality of clusters coupled to the first processor, wherein each cluster of the plurality of clusters comprises a plurality of core processors and a plurality of caches;
an interconnect interface that interconnects the clusters of the plurality of clusters;
a plurality of memory controllers coupled to the interconnect interface; and
a plurality of memories coupled to the memory controllers, wherein each memory of the plurality of memories comprises a plurality of bank groups;
wherein the system is configured to perform operations comprising:
receiving a plurality of memory requests comprising a plurality of addresses, wherein each memory request of the plurality of memory requests comprises a respective address of the plurality of addresses; and
hashing the addresses of the memory requests using a plurality of hashes to distribute the memory requests among the plurality of caches, the plurality of memory controllers, the plurality of memories, and the plurality of bank groups;
wherein each hash of the plurality of hashes is respectively programmed to achieve a specific distribution of the plurality of memory requests among the plurality of caches, the plurality of memory controllers, the plurality of memories, and the plurality of bank groups.

12. The system of claim 11 , wherein the hashes are programmed to achieve an even distribution of the plurality of memory requests across the plurality of clusters so that each cache of the plurality of caches receives a like number of the memory requests.

13. The system of claim 11 , wherein the plurality of hashes comprises a hash that is programmed to select a set of cache lines in a cache of the plurality of caches so that each set of cache lines in the cache receives a like number of the memory requests.

14. The system of claim 11 , wherein the hashes are programmed to achieve an even distribution of the plurality of memory requests across the plurality of controllers so that each memory controller of the plurality of memory controllers receives a like number of the memory requests.

15. The system of claim 11 , wherein the hashes are programmed to achieve an even distribution of the plurality of memory requests across the plurality of bank groups so that each bank group of the plurality of bank groups receives a like number of the memory requests.

16. The system of claim 11 , wherein the hashes are programmed to send a number of consecutive memory requests to a same memory controller of the plurality of memory controllers.

17. The system of claim 11 , wherein the hashes are programmed to send memory requests that have addresses within a specified address range to a same memory controller of the plurality of memory controllers.

18. The system of claim 11 , wherein the operations further comprise selecting a group of caches of the plurality of caches by hashing selected bits of a respective address of a memory request of the plurality of memory requests, wherein the selected bits are selected based on a specified distribution of a number of times each group of caches of the plurality of groups of caches is selected.

19. The system of claim 11 , wherein the plurality of hashes comprises:
a hash that is programmed to select a cache of the plurality of caches; and
a hash that is programmed to select a memory controller of the plurality of memory controllers that is closer to the cache than any other memory controller of the system.

20. The system of claim 11 , wherein the plurality of hashes comprises a hash that is programmed to select a bank group of the plurality of bank groups and select a bank in the bank group that is selected.

Assignees

• Marvell Asia Pte Ltd

Inventors

• Kessler Richard E
• Asher David
• Mukherjee Shubhendu S
• Snyder Ii Wilson P
• Carlson David
• Zebchuk Jason
• Akkawi Isam

Classifications

• G06F12/0844 Primary

  Multiple simultaneous or quasi-simultaneous cache accessing · CPC title

• G06F12/0813

  with a network or matrix configuration · CPC title

• G06F2212/1016

  Performance improvement · CPC title

• G06F2212/608

  Details relating to cache mapping · CPC title