Photonic systems to enable top-side wafer-level optical and electrical test

Patent metadata

Field	Value
Publication number	US-11867944-B2
Application number	US-202217701072-A
Country	US
Kind code	B2
Filing date	Mar 22, 2022
Priority date	Apr 23, 2019
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

An intact semiconductor wafer (wafer) includes a plurality of die. Each die has a top layer including routings of conductive interconnect structures electrically isolated from each other by intervening dielectric material. A top surface of the top layer corresponds to a top surface of the wafer. Below the top layer, each die has a device layer including optical devices and electronic devices. Each die has a cladding layer below the device layer and on a substrate of the wafer. Each die includes a photonic test port within the device layer. For each die, a light transfer region is formed within the intact wafer to extend through the top layer to the photonic test port within the device layer. The light transfer region provides a window for transmission of light into and out of the photonic test port from and to a location on the top surface of the wafer.

First claim

What is claimed is:

1. A semiconductor wafer, comprising:
a die including a device layer and a top layer formed over the device layer, the top layer having a substantially planar top surface on which a plurality of electrical contacts are exposed, the device layer formed over an optically reflective substrate with a cladding layer disposed between the device layer and the optically reflective substrate, the device layer including an optical device optically connected to a photonic test port, wherein the top layer includes a light transfer region configured to provide a window for optical coupling with the photonic test port from a location outside of the semiconductor wafer.

2. The semiconductor wafer as recited in claim 1 , wherein the light transfer region is a region of the top layer controlled to not include metal, and wherein a material of the top layer within the light transfer region allows for transmission of light.

3. The semiconductor wafer as recited in claim 1 , wherein the light transfer region is an open region formed in the top layer to expose the photonic test port.

4. The semiconductor wafer as recited in claim 1 , wherein at least a portion of the light transfer region and at least a portion of the photonic test port are formed in a kerf region along a side of the die.

5. The semiconductor wafer as recited in claim 1 , wherein the die includes a normal optical port and an optical switch, the optical switch having a first optical input optically connected to the photonic test port and a second optical input optically connected to the normal optical port, the optical switch having an optical output optically connected to the optical device, the optical switch configured to optically connect one of the photonic test port and the normal optical port to the optical output of the optical switch at a given time.

6. The semiconductor wafer as recited in claim 5 , wherein the normal optical port is configured to optically couple through the optically reflective substrate.

7. The semiconductor wafer as recited in claim 5 , wherein the optical switch is controllable through electronic signals.

8. The semiconductor wafer as recited in claim 5 , wherein the optical output port is optically connected to optical receiver circuitry within the device layer.

9. The semiconductor wafer as recited in claim 8 , wherein said optical switch is a first optical switch, the device layer including optical transmitter circuitry connected to the optical receiver circuitry, the device layer including a second optical switch having an optical input, a first optical output, and a second optical output, the optical input of the second optical switch optically connected to the optical transmitter circuitry, wherein said photonic test port is a first photonic test port, wherein said normal optical port is a first normal optical port, the device layer including a second photonic test port and a second normal optical port, the first optical output of the second optical switch optically connected to the second photonic test port, the second optical output of the second optical switch optically connected to the second normal optical port, the second optical switch configured to optically connect one of the second photonic test port and the second normal optical port to the optical input of the second optical switch at a given time.

10. The semiconductor wafer as recited in claim 9 , wherein each of the first normal optical port and the second normal optical port is configured to optically couple through the optically reflective substrate.

11. The semiconductor wafer as recited in claim 9 , wherein the first optical switch is controllable through a first electronic signal and the second optical switch is controllable through a second electronic signal.

12. The semiconductor wafer as recited in claim 8 , wherein said optical switch is a first optical switch, the device layer including optical transmitter circuitry connected to the optical receiver circuitry, the device layer including a second optical switch having an optical input, a first optical output, and a second optical output, the optical input of the second optical switch optically connected to the optical transmitter circuitry, wherein said normal optical port is a first normal optical port, the device layer including a second normal optical port and an optical waveguide, the first optical output of the second optical switch optically connected to the second normal optical port, the second optical output of the second optical switch optically connected to the optical waveguide, the second optical switch configured to optically connect one of the second normal optical port and the optical waveguide to the optical input of the second optical switch at a given time.

13. The semiconductor wafer as recited in claim 12 , wherein the device layer includes a third optical switch having a first optical input, a second optical input, and an optical output, the device layer including a third normal optical port, the first optical input of the third optical switch optically connected to the optical waveguide, the second optical input of the third optical switch optically connected to the third normal optical port, the third optical switch configured to optically connect one of the optical waveguide and the third normal optical port to the optical output of the third optical switch at a given time.

14. The semiconductor wafer as recited in claim 1 , wherein the device layer includes a plurality of photonic test ports, wherein said photonic test port is one of the plurality of photonic test ports, the device layer including an optical multiplexer having a first plurality of optical ports respectively optically connected to the plurality of photonic test ports, the optical multiplexer having a second plurality of optical ports, the device layer including a plurality of optical switches, each of the plurality of optical switches having a first optical port, a second optical port, and a third optical port, each of the plurality of optical switches configured to optically connect one of its first optical port and its second optical port to its third optical port at a given time, the device layer including a plurality of normal optical ports respectively optically connected to the first optical ports of the plurality of optical switches, the second plurality of optical ports of the optical multiplexer respectively optically connected to the second optical ports of the plurality of optical switches, the third optical ports of the plurality of optical switches optically connected to photonic circuitry within the device layer.

15. The semiconductor wafer as recited in claim 14 , wherein each of the plurality of normal optical ports is configured to optically couple through the optically reflective substrate.

16. The semiconductor wafer as recited in claim 14 , wherein each of the plurality of optical switches is controllable by a corresponding electronic signal.

17. The semiconductor wafer as recited in claim 1 , wherein the device layer includes electrical devices.

Assignees

• Ayar Labs Inc

Inventors

• Meade Roy Edward
• Sun Chen
• Ardalan Shahab
• Fini john
• Sedgwick Forrest

Classifications

• H10P74/27 Primary

  Structural arrangements therefor · CPC title

• H10P74/23

  characterised by multiple measurements, corrections, marking or sorting processes · CPC title

• H10P74/277

  Circuits for electrically characterising or monitoring manufacturing processes, e.g. circuits in tested chips or circuits in testing wafers · CPC title

• G02B6/12004 Primary

  Combinations of two or more optical elements · CPC title

• G01M11/31

  with a light emitter and a light receiver being disposed at the same side of a fibre or waveguide end-face, e.g. reflectometers · CPC title