Test method for control chip and related device

Patent metadata

Field	Value
Publication number	US-11867758-B2
Application number	US-202017595452-A
Country	US
Kind code	B2
Filing date	Oct 15, 2020
Priority date	Mar 11, 2020
Publication date	Jan 9, 2024
Grant date	Jan 9, 2024

Abstract

Embodiments of the present disclosure provide a test method and apparatus for a control chip, and an electronic device, which relate to the field of semiconductor device test technologies. The control chip includes a built-in self-test BIST circuit. The method is performed by the BIST circuit. The method includes: reading first test vectors stored in a first target memory chip; sending the first test vectors to the control chip; receiving first output information returned by the control chip in response to the first test vectors; and acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information. By means of the technical solutions provided in the embodiments of the present disclosure, so that a storage space for test vectors can be enlarged, and the test efficiency can be increased.

First claim

What is claimed is:

1. A test method for a control chip, the control chip comprising a built-in self-test (BIST) circuit, and the test method being performed by the BIST circuit, wherein the test method comprises:
acquiring a current status of a memory chip in a storage device;
using the memory chip in an idle state as a first target memory chip when the current status of the memory chip is the idle state, to store at least some of test vectors used for testing the control chip as first test vectors in the first target memory chip, wherein the idle state is a status of the memory chip when the memory chip currently has not stored any data;
reading the first test vectors stored in the first target memory chip;
sending the first test vectors to the control chip;
receiving first output information returned by the control chip in response to the first test vectors; and
acquiring a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information.

2. The test method for a control chip according to claim 1 , further comprising:
reading second test vectors stored in automatic test equipment (ATE);
sending the second test vectors to the control chip;
receiving second output information returned by the control chip in response to the second test vectors; and
acquiring a second test result of the control chip based on the second output information and the second test vectors corresponding to the second output information.

3. The test method for a control chip according to claim 1 , further comprising:
sending the first test result of the control chip to a second target memory chip for storage.

4. The test method for a control chip according to claim 3 , wherein the control chip, the first target memory chip, and the second target memory chip belong to a same storage device.

5. The test method for a control chip according to claim 4 , wherein the first target memory chip and the second target memory chip are vertically stacked in sequence on or under the control chip.

6. The test method for a control chip according to claim 3 , further comprising:
receiving a first control instruction sent by automatic test equipment (ATE);
reading the first test result of the control chip from the second target memory chip in response to the first control instruction; and
sending the first test result of the control chip to the ATE.

7. The test method for a control chip according to claim 1 , further comprising:
sending the first test result of the control chip to an automatic storage device for storage.

8. The test method for a control chip according to claim 1 , further comprising:
receiving a second control instruction sent by automatic test equipment (ATE); and
storing, in response to the second control instruction, the at least some of the test vectors used for testing the control chip as the first test vectors in the first target memory chip.

9. The test method for a control chip according to claim 1 , further comprising:
receiving a third control instruction sent by automatic test equipment (ATE);
testing the first target memory chip in response to the third control instruction; and
repairing the first target memory chip when the first target memory chip fails the test.

10. The test method for a control chip according to claim 1 , further comprising:
receiving a test instruction sent by automatic test equipment (ATE); and
testing a function of the BIST circuit in response to the test instruction.

11. The test method for a control chip according to claim 1 , further comprising:
receiving an initialization instruction sent by automatic test equipment (ATE); and
initializing the BIST circuit in response to the initialization instruction.

12. The test method for a control chip according to claim 1 , wherein the first target memory chip comprises a plurality of memory chips, and the plurality of memory chips are vertically stacked in sequence on or under the control chip.

13. The test method for a control chip according to claim 1 , wherein the first test vectors comprise any one of scan test vectors or function test vectors.

14. A test apparatus for a control chip, the control chip comprising a built-in self-test (BIST) circuit, and the BIST circuit comprising the test apparatus, wherein the test apparatus comprises:
a memory status acquiring circuit, configured to acquire a current status of a memory chip in a storage device;
a first memory determining circuit, configured to use the memory chip in an idle state as a first target memory chip when the current status of the memory chip is the idle state, to store at least some of test vectors used for testing the control chip as first test vectors in the first target memory chip, wherein the idle state is a status of the memory chip when the memory chip currently has not stored any data;
a first test vector reading circuit, configured to read the first test vectors stored in the first target memory chip;
a first test vector sending circuit, configured to send the first test vectors to the control chip;
a first output information receiving circuit, configured to receive first output information returned by the control chip in response to the first test vectors; and
a first test result acquiring circuit, configured to acquire a first test result of the control chip based on the first output information and the first test vectors corresponding to the first output information.

15. An electronic device, comprising:
one or more processors; and
a memory, configured to store one or more programs, wherein
the one or more programs, when executed by the one or more processors, cause the one or more processors to implement the test method according to claim 1 .

16. The test method for a control chip according to claim 8 , wherein storing, in response to the second control instruction, the at least some of the test vectors used for testing the control chip as the first test vectors in the first target memory chip comprises:
generating, in response to the second control instruction, the test vectors used for testing the control chip; and
storing the at least some of the test vectors used for testing the control chip as the first test vectors in the first target memory chip.

Assignees

• Changxin Memory Tech Inc

Inventors

• Shi Chuanqi
• Chang Heng-Chia
• Ding Li
• Liu Jie
• He Jun
• Ying Zhan

Classifications

• G01R31/3177 Primary

  Testing of logic operation, e.g. by logic analysers · CPC title

• G01R31/2834

  Automated test systems [ATE]; using microprocessors or computers (G01R31/317 takes precedence; ATE for detection of defective computer hardware G06F11/2736) · CPC title

• G01R31/2856

  Internal circuit aspects, e.g. built-in test features; Test chips; Measuring material aspects, e.g. electro migration [EM] · CPC title

• G01R31/3187

  Built-in tests · CPC title

• G01R31/3193

  with comparison between actual response and known fault free response {(receiver details G01R31/31924)} · CPC title