Integrated circuit and method capable of minimizing circuit area of non-volatile memory circuit

Patent metadata

Field	Value
Publication number	US-11863209-B2
Application number	US-202117405051-A
Country	US
Kind code	B2
Filing date	Aug 18, 2021
Priority date	Aug 18, 2021
Publication date	Jan 2, 2024
Grant date	Jan 2, 2024

Abstract

A method of integrated circuit includes: providing a non-volatile memory circuit for securely and permanently recording and protecting key data content having Y bits; providing a programmable memory circuit for storing user configuration data content having X bits greater than Y bits; converting the user configuration data content having X bits into user configuration key content having Y bits; comparing the user configuration key content having Y bits with the key data content having Y bits; selecting fallback configuration data content having X bits as output data when the user configuration key content does not match the key data content; selecting the user configuration data content having X bits as the output data when the user configuration key content matches the key data content; and receiving the output data of the decision circuit and performing at least one corresponding capability operation according to the output data.

First claim

What is claimed is:

1. An integrated circuit, comprising:
a non-volatile memory circuit, for securely and permanently recording and protecting a key data content having Y bits;
a programmable memory circuit, for storing a user configuration data content having X bits greater than Y bits;
a decision circuit, coupled to the non-volatile memory circuit and the programmable memory circuit, arranged for:
receiving the key data content having Y bits and the user configuration data content having X bits;
converting the user configuration data content having X bits into a user configuration key content having Y bits;
comparing the user configuration key content having Y bits with the key data content having Y bits;
selecting a fallback configuration data content having X bits as an output data when the user configuration key content does not match the key data content; and
selecting the user configuration data content having X bits as the output data when the user configuration key content matches the key data content; and

a processing circuit, coupled to the decision circuit, for receiving the output data of the decision circuit and performing at least one corresponding capability operation according to the output data.

2. The integrated circuit of claim 1 , wherein the decision circuit comprises:
a data compression circuit, for compressing the user configuration data content having X bits to generate the user configuration key content having Y bits smaller than X bits;
a comparator circuit, coupled to the data compression circuit, for comparing the user configuration key content having Y bits with the key data content having Y bits to generate a comparison signal; and
a multiplexer, coupled to the programmable memory circuit and the comparator circuit, for:
selecting the fallback configuration data content having X bits as the output data of the decision circuit when the comparison signal indicates that the user configuration key content does not match the key data content; and
selecting the user configuration data content having X bits as the output data when the comparison signal indicates that the user configuration key content matches the key data content.

3. The integrated circuit of claim 2 , wherein the data compression circuit employs a hamming code operation, a checksum operation, a cyclic redundancy check operation, or a hash algorithm.

4. The integrated circuit of claim 1 , wherein when the fallback configuration data is received, the at least one corresponding capability operation, performed by the processing circuit, comprises at least one of the followings: denying a system from functioning, partially disabling or crippling system capabilities, entering a special operating mode to inform a user of mismatch, and allowing the user to troubleshoot and correct a specific problem.

5. The integrated circuit of claim 4 , wherein after the specific problem is corrected, the decision circuit is arranged to select the user configuration data content having X bits as the output data.

6. The integrated circuit of claim 1 being synthesized as a netlist circuit or implemented as an application specific integrated circuit.

7. The integrated circuit of claim 1 being emulated by a programmable hardware circuit.

8. The integrated circuit of claim 1 being implemented by using discrete hardware components.

9. The integrated circuit of claim 1 being partially implemented by software components.

10. The integrated circuit of claim 1 , wherein the non-volatile memory circuit comprises a one-time-programmable read-only memory, an electrically-erasable programmable read-only memory, or a flash memory.

11. The integrated circuit of claim 1 , wherein the programmable memory circuit comprises a bank of flip-flops, a bank of latches, a register file, a static random access memory, or a dynamic random access memory.

12. A method of an integrated circuit, comprising:
providing a non-volatile memory circuit for securely and permanently recording and protecting a key data content having Y bits;
providing a programmable memory circuit for storing a user configuration data content having X bits greater than Y bits;
converting the user configuration data content having X bits into a user configuration key content having Y bits;
comparing the user configuration key content having Y bits with the key data content having Y bits;
selecting a fallback configuration data content having X bits as an output data when the user configuration key content does not match the key data content;
selecting the user configuration data content having X bits as the output data when the user configuration key content matches the key data content; and
receiving the output data of the decision circuit and performing at least one corresponding capability operation according to the output data.

13. The method of claim 12 , wherein the converting step comprises:
compressing the user configuration data content having X bits to generate the user configuration key content having Y bits smaller than X bits; and
the comparing step comprises:
using a comparator circuit to compare the user configuration key content having Y bits with the key data content having Y bits to generate a comparison signal.

14. The method of claim 13 , wherein the compressing step employs a hamming code operation, a checksum operation, a cyclic redundancy check operation, or a hash algorithm.

15. The method of claim 12 , wherein when the fallback configuration data is received, the method further comprises at least one of the followings: denying a system from functioning, partially disabling or crippling system capabilities, entering a special operating mode to inform a user of mismatch, and allowing the user to troubleshoot and correct a specific problem.

16. The method of claim 15 , further comprising:
after the specific problem is corrected, selecting the user configuration data content having X bits as the output data.

Assignees

• Pixart Imaging Inc

Inventors

• Chun Ee Wen
• Kong Shang Chan

Classifications

• H03M7/6041 Primary

  Compression optimized for errors · CPC title

• G11C17/12

  using field-effect devices · CPC title

• H03K19/1737 Primary

  using multiplexers (H03K19/1738 takes precedence) · CPC title

• H03M7/3055

  Conversion to or from Modulo-PCM · CPC title

• G11C17/16

  using electrically-fusible links · CPC title