Differential circuitry

Patent metadata

Field	Value
Publication number	US-11863199-B2
Application number	US-202217959887-A
Country	US
Kind code	B2
Filing date	Oct 4, 2022
Priority date	Oct 20, 2021
Publication date	Jan 2, 2024
Grant date	Jan 2, 2024

Abstract

Differential circuitry including first and second current paths each including a succession of first and further load nodes, each successive further load node connected to its preceding load node via a divider impedance; and first switching circuitry connected to the further load node or nodes of the first current path, and second switching circuitry connected to the further load node or nodes of the second current path, the first and second switching circuitry controlling a magnitude of controllable current signals passing through the load nodes of the first current path and the second current path, respectively, wherein: the first load nodes of the first and second current paths include a first pair of load nodes, and the or each successive further load node of the first current path and its corresponding successive further load node of the second current path include a successive further pair of load nodes.

First claim

The invention claimed is:

1. Differential circuitry comprising:
first and second current paths each comprising a succession of first and further load nodes, each successive further load node connected to its preceding load node via a divider impedance; and
first switching circuitry connected to the further load node or nodes of the first current path, and second switching circuitry connected to the further load node or nodes of the second current path, the first and second switching circuitry configured to control a magnitude of controllable current signals passing through the load nodes of the first current path and the second current path, respectively,
wherein:
the first load nodes of the first and second current paths comprise a first pair of load nodes, and the or each successive further load node of the first current path and its corresponding successive further load node of the second current path comprise a successive further pair of load nodes;
the first pair of load nodes are connected to a first common node via respective first load impedances and the or each successive further pair of load nodes are connected to a successive further common node via respective further load impedances;
the or each successive further common node is connected to its preceding common node; and
the or at least one of the successive further common nodes is connected to its preceding common node via a resistor.

2. The differential circuitry as claimed in claim 1 , wherein the or each other successive further common node is shorted to its preceding common node.

3. The differential circuitry as claimed in claim 1 , comprising N said successive further load nodes and N said successive further common nodes, wherein N is an integer greater than 1,
wherein:
for n of the successive further common node or nodes, the or each successive further common node is connected to its preceding common node via a resistor, wherein n is an integer and at least 1; and
for N-n of the successive further common node or nodes, the or each successive further common node is shorted to its preceding common node.

4. The differential circuitry as claimed in claim 3 , wherein:
n is 1 or N; or
n is 1≤n≤N.

5. The differential circuitry as claimed in claim 1 , wherein each successive further common node is connected to its preceding common node via a resistor.

6. The differential circuitry as claimed in claim 1 , wherein the resistors interconnecting said common nodes have the same resistance values as each other.

7. The differential circuitry as claimed in claim 1 , wherein the first load nodes are connected to first and second output nodes, respectively.

8. The differential circuitry as claimed in claim 7 , wherein the differential circuitry is configured to output a differential output signal between the first and second output nodes indicative of a differential input signal.

9. The differential circuitry as claimed in claim 8 , wherein the first switching circuitry and the second switching circuitry are configured to change the magnitude of the controllable current signals based on control signals indicative of the differential input signal.

10. The differential circuitry as claimed in claim 1 , wherein the first switching circuitry comprises a plurality of switches connected to the load nodes of the first current path, respectively, and wherein the second switching circuitry comprises a plurality of switches connected to the load nodes of the second current path, respectively.

11. The differential circuitry as claimed in claim 1 , wherein the first switching circuitry comprises a plurality of current sources connected to define respective currents at the switches of the first switching circuitry, respectively, and wherein the second switching circuitry comprises a plurality of current sources connected to define respective currents at the switches of the second switching circuitry, respectively.

12. The differential circuitry as claimed in claim 1 , wherein the first switching circuitry and the second switching circuitry comprise a plurality of current sources, each current source connected to define respective currents at the switches connected to a said pair of load nodes.

13. The differential circuitry as claimed in claim 1 , wherein the switches of the first switching circuitry are configured to be controlled by control signals indicative of a first input signal, and wherein the switches of the second switching circuitry are configured to be controlled by control signals indicative of a second input signal, the first and second input signals together corresponding to a differential input signal.

14. Digital-to-analogue converter, DAC, circuitry comprising the differential circuitry as claimed in claim 1 .

15. Integrated circuitry such as an IC chip, comprising the DAC circuitry as claimed in claim 14 .

16. Integrated circuitry such as an IC chip, comprising the differential circuitry as claimed in claim 1 .

Assignees

• Socionext Inc

Inventors

• Darzy Saul

Classifications

• H03M1/785 Primary

  using resistors, i.e. R-2R ladders · CPC title

• H03M1/747

  with equal currents which are switched by unary decoded digital signals · CPC title

• H03K17/60

  the devices being bipolar transistors (bipolar transistors having four or more electrodes H03K17/72) · CPC title

• H03M1/0658

  by calculating a running average of a number of subsequent samples · CPC title

• H03M1/66

  Digital/analogue converters ({H03M1/001 – } H03M1/10 take precedence) · CPC title