Oscillation circuit with improved failure detection

Patent metadata

Field	Value
Publication number	US-11863144-B2
Application number	US-202217652716-A
Country	US
Kind code	B2
Filing date	Feb 28, 2022
Priority date	Feb 28, 2022
Publication date	Jan 2, 2024
Grant date	Jan 2, 2024

Abstract

Apparatus and methods for non-invasively monitoring an oscillation signal in an effort to provide a more reliable oscillation signal. An example oscillation circuit generally includes an oscillator configured to generate an oscillation signal, the oscillator comprising an oscillator core circuit for coupling to a resonator and configured to generate the oscillation signal to enable the resonator to resonate and an adjustable current source coupled to the oscillator core circuit and configured to control an amplitude of the oscillation signal; a first automatic gain control (AGC) circuit having an input coupled to an output of the oscillator and having an output coupled to a control input of the adjustable current source; a second AGC circuit configured to replicate the first AGC circuit; and logic having a first input coupled to the output of the first AGC circuit and having a second input coupled to an output of the second AGC circuit.

First claim

What is claimed is:

1. An oscillation circuit comprising:
an oscillator configured to generate an oscillation signal, the oscillator comprising:
an oscillator core circuit for coupling to a resonator and configured to generate the oscillation signal to enable the resonator to resonate; and
an adjustable current source coupled to the oscillator core circuit and configured to control an amplitude of the oscillation signal;

a first automatic gain control (AGC) circuit having an input coupled to an output of the oscillator and having an output coupled to a control input of the adjustable current source;
a second AGC circuit configured to replicate the first AGC circuit such that the first AGC circuit is configured to generate a first reference signal and the second AGC circuit is configured to generate a second reference signal that replicates the first reference signal; and
logic having a first input coupled to the output of the first AGC circuit and having a second input coupled to an output of the second AGC circuit.

2. The oscillation circuit of claim 1 , wherein the logic is configured to effectively monitor the oscillation signal based on the output of the first AGC circuit and the output of the second AGC circuit.

3. The oscillation circuit of claim 1 , wherein the oscillation circuit is configured to effectively monitor the oscillation signal without directly sensing an amplitude of the oscillation signal.

4. The oscillation circuit of claim 1 , wherein the logic comprises a comparator having a first input coupled to the output of the first AGC circuit and having a second input coupled to the output of the second AGC circuit.

5. The oscillation circuit of claim 4 , wherein the comparator comprises:
a first p-type transistor having a source coupled to a power supply rail;
a first n-type transistor having a source coupled to a reference potential node for the oscillation circuit and having a drain coupled to a drain of the first p-type transistor, wherein at least one of the first p-type transistor or the first n-type transistor is tunable; and
an inverter having an input coupled to the drain of the first p-type transistor and to the drain of the first n-type transistor and having an output coupled to an output of the comparator.

6. The oscillation circuit of claim 5 , wherein the first AGC circuit comprises:
a second p-type transistor having a source coupled to the power supply rail;
a second n-type transistor having a source coupled to the reference potential node and having a drain coupled to a drain of the second p-type transistor;
a third p-type transistor having a source coupled to the power supply rail and having a gate coupled to a drain of the third p-type transistor, to a gate of the second p-type transistor, and to a gate of the first p-type transistor;
a third n-type transistor having a drain coupled to the drain and the gate of the third p-type transistor; and
a first resistive element coupled between a source of the third n-type transistor and the reference potential node.

7. The oscillation circuit of claim 6 , wherein the first AGC circuit further comprises:
a second resistive element coupled between a gate of the second n-type transistor and the drain of the second n-type transistor;
a third resistive element coupled between the drain of the second n-type transistor and a gate of the third n-type transistor; and
a first capacitive element coupled between the gate of the third n-type transistor and the reference potential node.

8. The oscillation circuit of claim 7 , further comprising a second capacitive element coupled between the gate of the second n-type transistor and the output of the oscillator.

9. The oscillation circuit of claim 7 , wherein the second n-type transistor, the third n-type transistor, the first resistive element, the second resistive element, and the third resistive element form at least part of a constant transconductance bias generator configured to generate a reference current that is dependent on process, voltage, and temperature (PVT).

10. The oscillation circuit of claim 6 , wherein a transistor size ratio between the first p-type transistor, the second p-type transistor, and the third p-type transistor is n:1:1, where n≥1.

11. The oscillation circuit of claim 6 , wherein:
the adjustable current source comprises a fourth p-type transistor having a source coupled to the power supply rail, having a drain coupled to the oscillator core circuit, and having a gate coupled to the gate of the second p-type transistor and to the third p-type transistor; and
a transistor size ratio between the fourth p-type transistor, the second p-type transistor, and the third p-type transistor is x:1:1, where x≥1.

12. The oscillation circuit of claim 6 , wherein the second AGC circuit comprises:
a fourth p-type transistor having a source coupled to the power supply rail;
a fourth n-type transistor having a source coupled to the reference potential node and having a drain coupled to a drain of the fourth p-type transistor, to a gate of the fourth n-type transistor, and to a gate of the first n-type transistor;
a fifth p-type transistor having a source coupled to the power supply rail and having a drain coupled to a gate of the fifth p-type transistor and to a gate of the fourth p-type transistor;
a fifth n-type transistor having a drain coupled to the drain and the gate of the fifth p-type transistor; and
a second resistive element coupled between a source of the fifth n-type transistor and the reference potential node.

13. The oscillation circuit of claim 12 , wherein a transistor size ratio between the first n-type transistor, the fourth n-type transistor, and the fifth n-type transistor is m:1:1, where m≥1.

14. The oscillation circuit of claim 13 , wherein a transistor size ratio between the first p-type transistor, the second p-type transistor, and the third p-type transistor is n:1:1, where n≥1.

15. The oscillation circuit of claim 14 , wherein a ratio of m/n is equal to a ratio of a gain of the second AGC circuit to a gain of the first AGC circuit.

16. The oscillation circuit of claim 15 , wherein:
the first AGC circuit comprises a constant transconductance bias generator configured to generate a reference current; and
the ratio of m/n is set such that the comparator is configured to output a logic high signal when the amplitude of the oscillation signal is estimated to be greater than or equal to an amplitude of the reference current multiplied by (1−m/n).

17. The oscillation circuit of claim 4 , wherein the comparator is configured to output a logic high signal when an amplitude of a signal at the output of the second AGC circuit is greater than or equal to an amplitude of a signal at the output of the first AGC circuit.

18. The oscillation circuit of claim 1 , wherein the first AGC circuit comprises a constant transconductance bias generator configured to generate a first reference current that is dependent on process, voltage, and temperature (PVT) of the first AGC circuit.

19. The oscillation circuit of claim 18 , wherein the second AGC circuit is configured to generate a second reference current that is equal to the first reference current.

20. The oscillation circuit of claim 1 , wherein an input of the second AGC circuit is open-circuited, such that the input of the second AGC circuit is configured to have zero current.

21. The oscillation circuit of claim 1 , further comprising:
a backup oscillator configured to generate anot

Assignees

• Qualcomm Inc

Inventors

• Iguchi Shunta
• Mehta Nikunj
• Farias Michael Naone

Classifications

• H04B17/318

  Received signal strength · CPC title

• H04B1/26

  for superheterodyne receivers (multiple frequency-changing H03D7/16) · CPC title

• H04B1/1607

  Supply circuits (converters H02M; filters therefor H02M1/14; voltage stabilisers G05F1/46) · CPC title

• H04B1/10

  Means associated with receiver for limiting or suppressing noise or interference · CPC title

• H03G3/3036 Primary

  in high-frequency amplifiers or in frequency-changers (H03G3/3052, H03G3/32, H03G3/34 take precedence) · CPC title