Methods of embedding magnetic structures in substrates

Patent metadata

Field	Value
Publication number	US-11862552-B2
Application number	US-202217567639-A
Country	US
Kind code	B2
Filing date	Jan 3, 2022
Priority date	Dec 27, 2017
Publication date	Jan 2, 2024
Grant date	Jan 2, 2024

Abstract

Methods/structures of forming embedded inductor structures are described. Embodiments include forming a first interconnect structure on a dielectric material of a substrate, selectively forming a magnetic material on a surface of the first interconnect structure, forming an opening in the magnetic material, and forming a second interconnect structure in the opening. Build up layers are then formed on the magnetic material.

First claim

What is claimed is:

1. A method of forming a microelectronic package structure, the method comprising:
forming a first interconnect structure on a dielectric material of a substrate;
selectively forming a magnetic material on a surface of the first interconnect structure;
forming a dielectric layer on the magnetic material;
grinding a first surface of the dielectric layer to be coplanar with a first surface of the magnetic material;
forming an opening in the magnetic material; and
forming a second interconnect structure in the opening.

2. The method of forming the microelectronic package structure of claim 1 , wherein
selectively forming the magnetic material comprises forming a sidewall of the magnetic material adjacent a sidewall of the first interconnect structure.

3. The method of forming the microelectronic package structure of claim 1 , wherein selectively forming the magnetic material comprises:
forming a dielectric layer on the first interconnect structure;
forming a cavity in the dielectric layer, wherein a surface of the first interconnect structure is exposed; and
forming the magnetic material in the cavity, and on the surface of the first interconnect structure.

4. The method of forming the microelectronic package structure of claim 1 , wherein selectively forming the magnetic material comprises:
forming the magnetic material on the surface of the first interconnect structure, wherein the magnetic material is formed on the dielectric material adjacent the first interconnect structure;
forming a mask on the surface of the first interconnect structure; and

plasma etching the magnetic material adjacent the mask.

5. The method of forming the microelectronic package structure of claim 4 , wherein forming the magnetic material comprises forming a magnetic film.

6. The method of forming the microelectronic package structure of claim 1 , wherein forming the first interconnect structure comprises forming a conductive pad, and wherein forming the second interconnect structure comprises forming a via.

7. The method of forming the microelectronic package of claim 1 wherein the magnetic material comprises one or more of nickel, iron or silicon, and alloys thereof.

Assignees

• Intel Corp

Inventors

• Vadlamani Sai
• Chatterjee Prithwish
• May Robert A
• Jain Rahul S
• Link Lauren A
• Brown Andrew J
• Lee Kyu Oh
• Li Sheng C

Classifications

• H10W90/754

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W90/725

  between a chip and a laterally-adjacent insulating package substrate, interposer or RDL · CPC title

• H10W90/724

  between a chip and a stacked insulating package substrate, interposer or RDL · CPC title

• H10W72/07236

  Soldering or alloying · CPC title

• H10W72/241

  Dispositions, e.g. layouts · CPC title