Determination of state metrics of memory sub-systems following power events

Patent metadata

Field	Value
Publication number	US-11862274-B2
Application number	US-202318116028-A
Country	US
Kind code	B2
Filing date	Mar 1, 2023
Priority date	Aug 18, 2020
Publication date	Jan 2, 2024
Grant date	Jan 2, 2024

Abstract

Disclosed is a system including a memory device having a plurality of physical cells and a processing device, operatively coupled with the memory device. The processing device maintains association of block families with a first (second, etc.) bin of a plurality of bins, each of the plurality of bins associated with one or more read voltage offsets. The read voltage offsets are used to compensate for a temporal read voltage shift caused by a charge loss by memory cells of the block families. Responsive to an occurrence of a power event, the processing device performs diagnostics of one or more blocks of various block families and determines whether to maintain association of the block families with current bins of the respective block families or to associate the block families with different bins.

First claim

What is claimed is:

1. A system comprising:
a memory device; and
a processing device, operatively coupled to the memory device, the processing device to perform operations comprising:
associating a first block family with a first bin of a plurality of bins, each of the plurality of bins associated with one or more read voltage offsets, wherein the read voltage offsets are to compensate for a temporal read voltage shift caused by a charge loss by memory cells of the first block family; and
responsive to an occurrence of a power event, performing diagnostics of one or more blocks of the first block family; and
based on results of the diagnostics, associating the first block family with a second bin of the plurality of bins.

2. The system of claim 1 , wherein all blocks of the first block family were programmed within a time interval not exceeding a threshold time.

3. The system of claim 1 , wherein a read voltage offset of the one or more read voltage offsets represents a correction to a read voltage applied during a read operation to a memory cell of a programmed block of the first block family.

4. The system of claim 3 , wherein the read voltage offset applied during the read operation of the memory cell depends on a charge state of the memory cell, the charge state being representative of data stored by the memory cell.

5. The system of claim 1 , wherein the power event comprises at least one of:
powering down of the memory device, or
powering up of the memory device.

6. The system of claim 1 , wherein a largest read voltage offset associated with the second bin is larger than a largest read voltage offset associated with the first bin.

7. The system of claim 1 , wherein the operations performed by the processing device further comprise:
responsive to the occurrence of the power event, performing diagnostics of one or more blocks of a second block family, wherein the second block family is associated with the first bin and comprises blocks programmed later than blocks of the first block family; and
based on results of the diagnostics, maintain association of the second block family with the first bin.

8. The system of claim 1 , wherein performing the diagnostics of the one or more blocks of the first block family comprises:
selecting a plurality of memory cells of the one or more blocks of the first block family; and
performing error count diagnostics of the selected plurality of memory cells.

9. The system of claim 8 , wherein the plurality of memory cells is selected randomly from memory cells of the one or more blocks of the first block family.

10. The system of claim 8 , wherein performing the error count diagnostics comprises:
identifying a read voltage offset corresponding to a minimum error count associated with the selected plurality of memory cells.

11. A method comprising:
associating, by a processing device operatively coupled with a memory device, a first block family of the memory device with a first bin of a plurality of bins, each of the plurality of bins associated with one or more read voltage offsets, wherein the read voltage offsets are to compensate for a temporal read voltage shift caused by a charge loss by memory cells of the first block family;
responsive to an occurrence of a power event, performing diagnostics of one or more blocks of the first block family; and
based on results of the diagnostics, associating the first block family with a second bin of the plurality of bins.

12. The method of claim 11 , wherein all blocks of the first block family were programmed within a time interval not exceeding a threshold time.

13. The method of claim 11 , wherein a read voltage offset of the one or more read voltage offsets represents a correction to a read voltage applied during a read operation to a memory cell of a programmed block of the first block family, and wherein the read voltage offset applied during the read operation of the memory cell depends on a charge state of the memory cell, the charge state being representative of data stored by the memory cell.

14. The method of claim 11 , wherein the power event comprises at least one of:
powering down of the memory device, or
powering up of the memory device.

15. The method of claim 11 , wherein a largest read voltage offset associated with the second bin is larger than a largest read voltage offset associated with the first bin.

16. The method of claim 11 , further comprising:
responsive to the occurrence of the power event, performing diagnostics of one or more blocks of a second block family, wherein the second block family is associated with the first bin and comprises blocks programmed later than blocks of the first block family; and
based on results of the diagnostics, maintaining association of the second block family with the first bin.

17. The method of claim 11 , wherein performing the diagnostics of the one or more blocks of the first block family comprises:
selecting a plurality of memory cells of the one or more blocks of the first block family; and
performing error count diagnostics of the selected plurality of memory cells.

18. The method of claim 17 , wherein the plurality of memory cells is selected randomly from memory cells of the one or more blocks of the first block family.

19. The method of claim 17 , wherein perform the error count diagnostics comprises:
identifying a read voltage offset corresponding to a minimum error count associated with the selected plurality of memory cells.

20. A non-transitory computer-readable memory storing instructions thereon that, when executed by a processing device, cause the processing device to perform operations comprising:
associating a first block family with a first bin of a plurality of bins, each of the plurality of bins associated with one or more read voltage offsets, wherein the read voltage offsets are to compensate for a temporal read voltage shift caused by a charge loss by memory cells of the first block family; and
responsive to an occurrence of a power event, performing diagnostics of one or more blocks of the first block family; and
based on results of the diagnostics, associating the first block family with a second bin of the plurality of bins.

Assignees

• Micron Technology Inc

Inventors

• Sheperek Michael
• Liikanen Bruce A
• Kientz Steven Michael

Classifications

• G11C29/44 Primary

  Indication or identification of errors, e.g. for repair · CPC title

• G11C29/12005

  comprising voltage or current generators · CPC title

• G11C29/12015

  comprising clock generation or timing circuitry · CPC title

• G11C29/42

  using error correcting codes [ECC] or parity check · CPC title

• G11C2029/0407

  on power on · CPC title