Memory and method for writing memory

Patent metadata

Field	Value
Publication number	US-11862237-B2
Application number	US-202217659951-A
Country	US
Kind code	B2
Filing date	Apr 20, 2022
Priority date	Jul 8, 2021
Publication date	Jan 2, 2024
Grant date	Jan 2, 2024

Abstract

A memory includes a bank, the bank includes a plurality of sections, each of the plurality of section includes a plurality of word lines, a plurality of bit lines, and a plurality of storage units arranged in an array, and each of the plurality of storage units is connected to one of the plurality of word lines and one of the plurality of bit lines; the bank is configured to: in a preset mode, in response to a control signal, activate each of a plurality of word lines in at least one target section of the bank, pull up or pull down a level of each of a plurality of bit lines in the target section, and pull a complementary bit line of each of the plurality of bit lines in the target section to a level opposite to a level of the plurality of bit lines.

First claim

What is claimed is:

1. A memory, comprising:
a bank, wherein
the bank comprises a plurality of sections, each of the plurality of sections comprises a plurality of word lines, a plurality of bit lines, and a plurality of storage units arranged in an array, each of the plurality of storage units being connected to one of the plurality of word lines and one of the plurality of bit lines; and
the bank is configured to: in a preset mode, in response to a control signal, activate each of a plurality of word lines in at least one target section of the bank, pull up or pull down a level of each of a plurality of bit lines in the target section, and pull a complementary bit line of each of the plurality of bit lines in the target section to a level opposite to a level of the plurality of bit lines, wherein the complementary bit line is a bit line in a section adjacent to the target section.

2. The memory of claim 1 , wherein the memory further comprises a bit-line write control circuit; wherein the bit-line write control circuit is configured to pull up or pull down a level of all the plurality of bit lines in the target section based on the control signal.

3. The memory of claim 2 , wherein the bit-line write control circuit comprises an enable circuit and a bit-line write circuit; wherein the enable circuit is configured to: output a bit-line write control signal to the bit-line write circuit, the bit-line write control signal being a high write control signal or a low write control signal, and wherein the bit-line write circuit is configured to pull the bit line to a high level or a low level based on the bit-line write control signal.

4. The memory of claim 3 , wherein the enable circuit comprises a first AND gate; wherein the first AND gate is configured to output the bit-line write control signal based on a section enable signal.

5. The memory of claim 4 , wherein the bit-line write circuit comprises a first transistor and a second transistor;
wherein the first transistor is turned on in response to the low write control signal, and the second transistor is turned on in response to the high write control signal, and wherein a source of the first transistor is coupled to a power terminal, a drain of the first transistor is coupled to a drain of the second transistor, a source of the second transistor is grounded, and a gate of the first transistor is connected to a gate of the second transistor and is coupled to the first AND gate; or
wherein the first transistor and the second transistor are turned on in response to the low write control signal, and wherein the source of the first transistor is coupled to the power terminal, the drain of the first transistor is coupled to the plurality of bit lines, the source of the second transistor is coupled to the complementary bit line, the drain of the second transistor is grounded, and the gate of the first transistor is connected to the gate of the second transistor and is coupled to the first AND gate; or
wherein the first transistor and the second transistor are turned on in response to the high write control signal, and wherein the drain of the first transistor is coupled to the power terminal, the source of the first transistor is coupled to the plurality of bit lines, the drain of the second transistor is coupled to the complementary bit line, the source of the second transistor is grounded, and the gate of the first transistor is connected to the gate of the second transistor and is coupled to the first AND gate.

6. The memory of claim 4 , wherein the bit-line write control circuit further comprises a complementary bit-line write circuit; wherein the complementary bit-line write circuit is configured to pull the complementary bit line to the level opposite to the level of the plurality of bit lines in the target section.

7. The memory of claim 6 , wherein the enable circuit further comprises a second AND gate; wherein the second AND gate is configured to output a complementary bit-line write control signal to the complementary bit-line write circuit based on the control signal, the complementary bit-line write control signal being a high write control signal or a low write control signal; and wherein the complementary bit-line write circuit is configured to pull the complementary bit line to a high level or a low level based on the complementary bit-line write control signal.

8. The memory of claim 7 , wherein the second AND gate is configured to output the low write control signal, in response to the first AND gate outputting the high write control signal, and wherein the first AND gate is configured to output the high write control signal, in response to the second AND gate outputting the low write control signal.

9. The memory of claim 8 , wherein the complementary bit-line write circuit comprises a third transistor and a fourth transistor;
wherein the third transistor is turned on in response to the low write control signal, and the fourth transistor is turned on in response to the high write control signal, and wherein a source of the third transistor is coupled to a power terminal, a drain of the third transistor is coupled to a drain of the fourth transistor, a source of the fourth transistor is grounded, and a gate of the third transistor is connected to a gate of the fourth transistor and is coupled to the second AND gate; or
wherein the third transistor and the fourth transistor are turned on in response to the low write control signal, and wherein the source of the third transistor is coupled to the complementary bit line, the drain of the third transistor is grounded, the source of the fourth transistor is coupled to the power terminal, the drain of the fourth transistor is coupled to the complementary bit line, and the gate of the third transistor is connected to the gate of the fourth transistor and is coupled to the second AND gate; or
wherein the third transistor and the fourth transistor are turned on in response to the high write control signal, and wherein the drain of the third transistor is coupled to the complementary bit line, the source of the third transistor is grounded, the drain of the fourth transistor is coupled to the power terminal, the source of the fourth transistor is coupled to the complementary bit line, and the gate of the third transistor is connected to the gate of the fourth transistor and is coupled to the second AND gate.

10. The memory of claim 6 , wherein the bank further comprises an isolation circuit; wherein the isolation circuit comprises a first switch transistor connected between the plurality of bit lines and the bit-line write circuit, and a second switch transistor connected between the complementary bit line and the complementary bit-line write circuit.

11. The memory of claim 10 , wherein in response to the preset mode being a compression write mode, the isolation circuit is configured to turn on the first switch transistor and the second switch transistor; and in response to the preset mode being not the compression write mode, the isolation circuit is configured to turn off the first switch transistor and the second switch transistor.

12. The memory of claim 11 , wherein a gate of the first switch transistor is connected to a gate of the second switch transistor and is coupled to an isolation signal terminal; wherein in response to the preset mode being the compression write mode, the isolation signal terminal is configured to output a high-level signal to the first switch transistor and the second switch transistor; and in response to the preset mode being not the compression write mode, the isolation signal terminal is configured to output a low-level signal to the first switch tran

Assignees

• Changxin Memory Tech Inc

Inventors

• Lu Tianchen

Classifications

• G11C11/4096 Primary

  Input/output [I/O] data management or control circuits, e.g. reading or writing circuits, I/O drivers or bit-line switches · CPC title

• G11C11/4085

  Word line control circuits, e.g. word line drivers, - boosters, - pull-up, - pull-down, - precharge · CPC title

• G11C11/4094

  Bit-line management or control circuits · CPC title

• H03K19/01742 Primary

  by means of a pull-up or down element · CPC title

• H03K19/018521

  of complementary type, e.g. CMOS · CPC title