Power supply circuit and memory

Patent metadata

Field	Value
Publication number	US-11862228-B2
Application number	US-202217668638-A
Country	US
Kind code	B2
Filing date	Feb 10, 2022
Priority date	Jul 16, 2021
Publication date	Jan 2, 2024
Grant date	Jan 2, 2024

Abstract

A power supply circuit and a memory are provided. The power supply circuit includes a voltage source, multiple power supply circuits and a control circuit. The multiple power supply circuits are connected to the voltage source. If the voltage source is effective and the multiple power supply circuits are in an enable state, a voltage of a power supply terminal is pulled up to a preset voltage, and power is supplied to the load units during the pulling up process. A first-type power circuit enters the enable state if a first enable signal is received, and each of second-type power supply circuits enters the enable state if second enable signal is received.

First claim

The invention claimed is:

1. A power supply circuit, comprising:
a voltage source and multiple power supply circuits connected to the voltage source, wherein the multiple power supply circuits have power supply terminals and load units, and when the voltage source is effective and the multiple power supply circuits are in an enable state, the multiple power supply circuits pull up voltages of the power supply terminals to a preset voltage, and supply power to the load units during the pulling up process,
wherein the multiple the power supply circuits comprise at least one first-type power supply circuit and second-type power supply circuits, the first-type power supply circuit is configured to receive a first enable signal, and enter the enable state when the first enable signal is received, and each of the second-type power supply circuits is configured to receive a second enable signal, and enter the enable state when the second enable signal is received; and
a control circuit configured to: receive a flag signal, and transmit the first enable signal to the first-type power supply circuit when the received flag signal is in an effective state, wherein the effective state characterizes an effectiveness of the voltage source,
wherein the control circuit is further configured to: receive a plurality of external signals after transmitting the first enable signal, each of the external signals corresponding to one of the second-type power supply circuits and start times of different external signals being different; and transmit a second enable signal to a corresponding second-type power supply circuit when the flag signal and an external signal are received.

2. The power supply circuit of claim 1 , wherein the control circuit comprises a first enable unit and a plurality of second enable units, an output terminal of each of the second enable units is connected to an enable terminal of a corresponding second-type power supply circuit, the first enable unit is configured to receive the flag signal, and transmit the first enable signal after the flag signal reaches the effective state, each second enable unit is configured to receive the flag signal and an external signal and transmit a second enable signal, and the external signals received by different second enable units are different.

3. The power supply circuit of claim 2 , wherein the flag signal, the external signals, the first enable signal and the second enable signals are high-level effective signals.

4. The power supply circuit of claim 3 , wherein each second enable unit comprises an SR latch.

5. The power supply circuit of claim 4 , wherein the SR latch comprises a first NOR gate and a second NOR gate, a first input terminal of the first NOR gate being configured to receive the external signal, a second input terminal of the first NOR gate being connected to an output terminal of the second NOR gate, an output terminal of the first NOR gate being connected to a first input terminal of the second NOR gate, a second input terminal of the second NOR gate being configured to receive the flag signal, the output terminal of the second NOR gate serving as an output terminal of the second enable unit, and the output terminal of the second NOR gate being configured to output the second enable signal.

6. The power supply circuit of claim 1 , wherein the external signals comprise anti-fuse address signals, and start times of different anti-fuse address signals are different.

7. The power supply circuit of claim 6 , wherein the control circuit is further configured to receive m first anti-fuse address signals and select n second anti-fuse address signals from the m first anti-fuse address signals, intervals between start times of adjacent second anti-fuse address signals are the same, the intervals between the start times of adjacent second anti-fuse address signals are greater than intervals between start times of the adjacent first anti-fuse address signals, and the second anti-fuse address signals are used as the external signals.

8. The power supply circuit of claim 6 , wherein the control circuit is further connected to an anti-fuse scanning unit, the anti-fuse scanning unit is configured to scan address information of an anti-fuse array and generate the anti-fuse address signals, and the control circuit is configured to receive the anti-fuse address signals generated by the anti-fuse scanning unit.

9. The power supply circuit of claim 8 , wherein the anti-fuse scanning unit is further configured to receive a reset signal, the reset signal is configured to trigger the anti-fuse scanning unit to scan the address information of the anti-fuse array, and a reception time of the reset signal is later than a reception time of the effective state of the flag signal.

10. The power supply circuit of claim 8 , wherein the control circuit is further configured to connect to the anti-fuse scanning unit through a local latch, the anti-fuse scanning unit is further configured to transmit the generated anti-fuse address signals to the local latch, and the control circuit is further configured to receive the anti-fuse address signals from the local latch.

11. The power supply circuit of claim 1 , wherein the load units comprise filter capacitors.

12. The power supply circuit of claim 1 , wherein the control circuit is configured to transmit the first enable signal and the second enable signals before generation of a clock enable signal to enable the first-type power supply circuit and the second-type power supply circuits.

13. A memory comprising a power supply circuit, wherein the power supply circuit comprises:
a voltage source and multiple power supply circuits connected to the voltage source, wherein the multiple power supply circuits have power supply terminals and load units, and when the voltage source is effective and the multiple power supply circuits are in an enable state, the multiple power supply circuits pull up voltages of the power supply terminals to a preset voltage, and supplies power to the load units during the pulling up process,
wherein the multiple the power supply circuits comprise at least one first-type power supply circuit and second-type power supply circuits, the first-type power supply circuit is configured to receive a first enable signal, and enter the enable state when the first enable signal is received, and each of the second-type power supply circuits is configured to receive a second enable signal, and enter the enable state when the second enable signal is received; and
a control circuit configured to: receive a flag signal, and transmit the first enable signal to the first-type power supply circuit when the received flag signal is in an effective state, wherein the effective state characterizes an effectiveness of the voltage source,
wherein the control circuit is further configured to: receive a plurality of external signals after transmitting the first enable signal, each of the external signals corresponding to one of the second-type power supply circuits and start times of different external signals being different; and transmit a second enable signal to a corresponding second-type power supply circuit when the flag signal and an external signal are received.

14. The memory of claim 13 , wherein the power supply circuit is located in a peripheral circuit area between adjacent memory banks.

15. The memory of claim 14 , wherein a plurality of power supply circuits are evenly distributed in an extension direction of the peripheral circuit area.

16. The memory of claim 13 , wherein the control circuit comprises a first enable unit and

Assignees

• Changxin Memory Tech Inc

Inventors

• Ji Rumin

Classifications

• G11C11/4074 Primary

  Power supply or voltage generation circuits, e.g. bias voltage generators, substrate voltage generators, back-up power, power control circuits · CPC title

• G11C11/4072

  Circuits for initialization, powering up or down, clearing memory or presetting · CPC title

• G11C5/145

  Applications of charge pumps; Boosted voltage circuits; Clamp circuits therefor (G11C5/141 takes precedence) · CPC title