Masked gate logic for resistance to power analysis

Patent metadata

Field	Value
Publication number	US-11861047-B2
Application number	US-202217862134-A
Country	US
Kind code	B2
Filing date	Jul 11, 2022
Priority date	Dec 12, 2013
Publication date	Jan 2, 2024
Grant date	Jan 2, 2024

Abstract

A method of and system for gate-level masking of secret data during a cryptographic process is described. A mask share is determined, wherein a first portion of the mask share includes a first number of zero-values and a second number of one-values, and a second portion of the mask share includes the first number of one-values and the second number of zero-values. Masked data values and the first portion of the mask share are input into a first portion of masked gate logic, and the masked data values and the second portion of the mask share are input into a second portion of the masked gate logic. A first output from the first portion of the masked gate logic and a second output from the second portion of the masked gate logic are identified, wherein either the first output or the second output is a zero-value.

First claim

What is claimed is:

1. A cryptographic circuit comprising:
Boolean logic circuitry to receive cipher input values and masking values, wherein the Boolean logic circuitry outputs masked data values;
a data store to store a mask share, wherein a first portion of the mask share comprises a first number of zero-values and a second number of one-values, and a second portion of the mask share comprises the first number of one-values and the second number of zero-values; and
masked gate logic circuitry coupled to the data store and the Boolean logic circuitry, wherein the masked gate logic circuitry comprising:
a first portion to receive the masked data values and the first portion of the mask share and provide a first output; and
a second portion to receive the masked data values and the second portion of the mask share and provide a second output.

2. The cryptographic circuit of claim 1 , further comprising a mask generator circuit to determine the mask share.

3. The cryptographic circuit of claim 1 , wherein:
the first portion of the masked gate logic circuitry comprises a first four AND gates and a first OR gate, the first OR gate to receive outputs of the first four AND gates; and
the second portion of the masked gate logic circuitry comprises a second four AND gates and a second OR gate, the second OR gate to receive outputs of the second four AND gates.

4. The cryptographic circuit of claim 1 , further comprising additional logic circuitry coupled to the masked gate logic circuitry, wherein the additional logic circuitry is to determine a final output based on the first output and the second output, wherein the final output is independent of secret data that is masked in the masked data values.

5. The cryptographic circuit of claim 1 , further comprising additional logic circuitry coupled to the masked gate logic circuitry, wherein the additional logic circuitry is to perform an additional function on the first output and the second output before outputting a final output, wherein the final output is independent of secret data that is masked in the masked data values.

6. The cryptographic circuit of claim 1 , wherein the data store comprises a first-in-first-out (FIFO) buffer.

7. A circuit comprising:
Boolean logic circuitry to receive cipher input values and masking values, wherein the Boolean logic circuitry outputs masked data values;
a mask generator circuit to determine a mask share, wherein a first portion of the mask share comprises a first number of zero-values and a second number of one-values, and a second portion of the mask share comprises the first number of one-values and the second number of zero-values;
a data store to store the mask share; and
masked gate logic circuitry coupled to the mask generator circuit, the Boolean logic circuitry, and the data store, wherein the masked gate logic circuitry comprises:
a first circuit to:
receive the masked data values from the Boolean logic circuitry;
receive the first portion of the mask share from the mask generator circuit; and
provide a first output;

a second circuit to:
receive the masked data values from the Boolean logic circuitry;
receive the second portion of the mask share from the mask generator circuit; and
provide a second output.

8. The circuit of claim 7 , further comprising additional Boolean logic circuitry coupled to the masked gate logic circuitry, the additional Boolean logic circuitry to:
receive the first output from the first portion of the masked gate logic circuitry;
receive the second output from the second portion of the masked gate logic circuitry; and
provide cipher output values.

9. The circuit of claim 7 , wherein the mask generator circuit comprises:
a random number generator coupled to the Boolean logic circuitry, the random number generator to generate the masking values; and
a table generator coupled to the random number generator, the table generator to generate the mask share, the table generator to store the mask share in the data store.

10. The circuit of claim 7 , wherein the data store comprises a first-in-first-out (FIFO) buffer.

11. The circuit of claim 7 , wherein the first portion of the masked gate logic circuitry comprises a first four AND gates and a first OR gate, the first OR gate to receive outputs of the first four AND gates, and wherein the second portion of the masked gate logic circuitry comprises a second four AND gates and a second OR gate, the second OR gate to receive outputs of the second four AND gates.

12. The circuit of claim 7 , further comprising additional logic circuitry coupled to the masked gate logic circuitry, wherein the additional logic circuitry is to determine a final output based on the first output and the second output, wherein the final output is independent of the cipher input values.

13. The circuit of claim 7 , further comprising additional logic circuitry coupled to the masked gate logic circuitry, wherein the additional logic circuitry is to perform an additional function on the first output and the second output before outputting a final output, wherein the final output is independent of the cipher input values.

14. The circuit of claim 7 , wherein the data store is to store the mask share for one or more clock cycles prior to the first portion of the masked gate logic circuitry receiving the masked data values and the first portion of the mask share.

15. The circuit of claim 7 , wherein the masked gate logic circuitry is to receive precharge signals during a first stage of a cryptographic operation, wherein the masked generator circuit is to determine the mask share during a second stage of the cryptographic operation, wherein the masked gate logic circuitry is to receive the masked data values and the mask share during a third stage of the cryptographic operation, and wherein the masked gate logic circuitry is to output the first portion and the second portion during a fourth stage of the cryptographic operation.

16. A system comprising:
an integrated circuit comprising a set of propagation paths and a cryptographic circuit to perform a cryptographic operation; and
a power delivery network coupled to the integrated circuit, the power delivery network to deliver power to the integrated circuit, wherein the cryptographic circuit comprises:
a data store to store a mask share;
masked gate logic circuitry to output output signals on each of the set of propagation paths with equal probability during the cryptographic operation to mask secret data from being detected via power analysis of the power delivery network with at least a portion of the mask share; and
additional logic circuitry coupled to the masked gate logic circuitry, wherein the additional logic circuitry is to determine a final output based on a first output and a second output of the output signals, wherein the final output is independent of secret data that is masked in the masked data values.

17. The system of claim 16 , wherein the masked gate logic circuitry comprises:
a first portion to receive masked data values and a first portion of the mask share, the first portion to provide the first output, wherein the masked data values correspond to the secret data being masked by masking values; and
a second portion to receive the masked data values and a second portion of the mask share, the second portion to provide the second output.

18. The system of claim 17 , wherein the first portion of the masked gate logic circuitry comprises a first four AND gates and a first OR gate, the first OR gate to receive outputs o

Assignees

• Cryptography Res Inc

Inventors

• Leiserson Andrew John
• Marson Mark Evan
• Wachs Megan Anneke

Classifications

• G06F21/72 Primary

  in cryptographic circuits · CPC title

• G06F21/71 Primary

  to assure secure computing or processing of information · CPC title

• G06F21/755

  with measures against power attack · CPC title

• H04L9/003

  for power analysis, e.g. differential power analysis [DPA] or simple power analysis [SPA] · CPC title

• H04L2209/04

  Masking or blinding · CPC title