Semiconductor device, control flow inspection method, non-transitory computer readable medium, and electronic device

Patent metadata

Field	Value
Publication number	US-11860762-B2
Application number	US-201917618930-A
Country	US
Kind code	B2
Filing date	Jun 25, 2019
Priority date	Jun 25, 2019
Publication date	Jan 2, 2024
Grant date	Jan 2, 2024

Abstract

A semiconductor device ( 100 ) includes: first storage means ( 110 ) storing, in advance, a plurality of pieces of execution order inspection information ( 111˜11 n ) used for inspection of an execution order of a plurality of code blocks in a predetermined program, second storage means ( 120 ), which is a cache for the first storage means, and prediction means ( 130 ) for predicting a storage area of the execution order inspection information based on prediction auxiliary information in a first code block of the plurality of code blocks and a control flow graph of the program, the storage area being a prefetch target to be prefetched from the first storage means to the second storage means.

First claim

What is claimed is:

1. A semiconductor device comprising:
first storage apparatus configured to store, in advance, a plurality of pieces of execution order inspection information used for inspection of an execution order of a plurality of code blocks in a predetermined program;
second storage apparatus, which is a cache for the first storage apparatus;
at least one memory configured to store instructions, and
at least one processor configured to execute the instructions to:
predict a storage area of the execution order inspection information based on prediction auxiliary information in a first code block of the plurality of code blocks and a control flow graph of the program, the storage area being a prefetch target to be prefetched from the first storage apparatus to the second storage apparatus, and the storage area being predicted as the prefetch target in accordance with execution of an inspection instruction of control flow integrity configured in the first code block;
prefetch the predicted storage area from the first storage apparatus to the second storage apparatus;
determine, at a time of execution of an inspection instruction of control flow integrity configured in a third code block that has been executed after the first code block, an access destination to be one of the first storage apparatus and the second storage apparatus based on the prediction auxiliary information in the third code block, and acquire first execution order inspection information that corresponds to the current execution order of the third code block from the determined access destination; and
calculate second execution order inspection information that corresponds to the current execution order of the third code block and inspect whether it is possible to execute a code block executed after the third code block in accordance with the result of comparing the acquired first execution order inspection information with the calculated second execution order inspection information.

2. The semiconductor device according to claim 1 , wherein the at least one processor further configured to execute the instructions to
specify a second code block that may be executed after the first code block based on the prediction auxiliary information and the control flow graph;
specify a path of a control flow from the first code block to the second code block; and
predict the storage area of the execution order inspection information that corresponds to the specified path as the prefetch target.

3. The semiconductor device according to claim 2 , wherein the at least one processor further configured to execute the instructions to
specify a first position of the first code block in the program based on the control flow graph; and
specify a second position included in a control flow from the first position as the second code block based on the result of the analysis of the prediction auxiliary information and the control flow graph.

4. The semiconductor device according to claim 2 , wherein the at least one processor further configured to execute the instructions to
predict, when the execution frequency of the specified path is higher than those of other paths that may be executed by being branched off from the first code block, the storage area of the execution order inspection information that corresponds to the specified path as the prefetch target.

5. The semiconductor device according to claim 2 , wherein the at least one processor further configured to execute the instructions to
predict, when the number of code blocks included in the specified path is equal to or larger than a predetermined value, the storage area of the execution order inspection information that corresponds to the specified path as the prefetch target.

6. The semiconductor device according to claim 2 , wherein the at least one processor further configured to execute the instructions to
specify the path so as to include three or more code blocks.

7. The semiconductor device according to claim 1 , wherein the prediction auxiliary information includes at least one of an input value to the first code block, an internal state variable value at the time of execution of the first code block, and the priority of execution of paths that may be executed by being branched off from the first code block.

8. The semiconductor device according to claim 1 , wherein the execution order inspection information includes a hash value calculated based on a path of a control flow regarding two or more of the plurality of code blocks.

9. The semiconductor device according to claim 1 , wherein
the semiconductor device includes a secure area and a non-secure area,
the secure area includes the at least one memory, the first storage apparatus, the second storage apparatus, a prediction circuitry, an inspection circuitry, and
the non-secure area includes the at least one processor,
the prediction circuitry configured to predict, in accordance with the execution of the inspection instruction by the at least one processor, the prefetch target in accordance with a fourth code block in which the inspection instruction is set, prefetch the prefetch target, determine an access destination to be one of the first storage apparatus and the second storage apparatus based on the prediction auxiliary information in the fourth code block, and acquire third execution order inspection information that corresponds to the current execution order of the fourth code block from the determined access destination, and
the inspection circuitry configured to inspect whether it is possible to execute a code block executed after the code block in which the inspection instruction is set in accordance with the execution of the inspection instruction by the at least one processor.

10. An electronic device comprising the semiconductor device according to claim 1 .

11. A control flow inspection method, wherein
a computer comprising:
first storage apparatus for storing, in advance, a plurality of pieces of execution order inspection information used for inspection of an execution order of a plurality of code blocks in a predetermined program; and
second storage apparatus, which is a cache for the first storage apparatus,
acquires prediction auxiliary information in a first code block of the plurality of code blocks and a control flow graph of the program;
predicts a storage area of the execution order inspection information based on the prediction auxiliary information and the control flow graph, the storage area being a prefetch target to be prefetched from the first storage apparatus to the second storage apparatus, and the storage area being predicted as the prefetch target in accordance with execution of an inspection instruction of control flow integrity configured in the first code block;
prefetches the predicted storage area from the first storage apparatus to the second storage apparatus;
determines, at a time of execution of an inspection instruction of control flow integrity configured in a third code block that has been executed after the first code block, an access destination to be one of the first storage apparatus and the second storage apparatus based on the prediction auxiliary information in the third code block, and acquire first execution order inspection information that corresponds to the current execution order of the third code block from the determined access destination; and
calculates second execution order inspection information that corresponds to the current execution order of the third code block and inspect whether it is possible to execute a code block executed after the third code block in accordance with the result of comparing the acquired first execution

Assignees

• Nec Corp

Inventors

• JADA Astha
• Kobayashi Toshiki
• Sasaki Takayuki
• ASONI Daniele Enrico
• Perrig Adrian

Classifications

• G06F11/3612 Primary

  by runtime analysis (performance monitoring G06F11/3466) · CPC title

• G06F11/3688

  for test execution, e.g. scheduling of test suites · CPC title