Method and apparatus for performing power stress test on FPGA acceleration card, and storage medium

Patent metadata

Field	Value
Publication number	US-11860747-B2
Application number	US-202118012923-A
Country	US
Kind code	B2
Filing date	May 27, 2021
Priority date	Aug 7, 2020
Publication date	Jan 2, 2024
Grant date	Jan 2, 2024

Abstract

A method and apparatus for performing a power stress test on an FPGA acceleration card and a computer-readable storage medium. The method includes: dividing, according to a partial reconfiguration method, a hardware resource of an FPGA acceleration card into a static region serving as a hardware logic implementation region for performing a normal function test, and a dynamic PR region including a blank mode occupying no hardware resource and a power test mode for performing a power stress test, and burning FPGA firmware having a partial reconfiguration function to a flash memory; upon receiving a request for power stress test, configuring an operation mode of the dynamic PR region to be the power test mode, loading, to the dynamic PR region, a dynamic PR configuration file burned in the flash memory; and calling a power stress test module to execute the power stress test in the dynamic PR region.

First claim

The invention claimed is:

1. A method for performing a power stress test on a field programmable gate array (FPGA) acceleration card, comprising:
dividing, according to a partial reconfiguration (PR) method, the FPGA acceleration card into a static region and a dynamic PR region in advance, and burning FPGA firmware with a partial reconfiguration function to a Flash memory;
in response to receiving a request for power stress test, setting an operating mode of the dynamic PR region as a power test mode, and loading dynamic PR profiles burned in the Flash memory to the dynamic PR region; and
calling power stress test modules to perform the power stress test in the dynamic PR region, wherein
the static region is a hardware logic implementation region for a functional test other than the power stress test, the dynamic PR region comprises a blank mode occupying no hardware resource and the power test mode for performing the power stress test, and the dynamic PR region in the blank mode is used for performing a test other than the power stress test in conjunction with the static region.

2. The method according to claim 1 , further comprising:
in response to receiving an instruction for configuring power stress test modules transmitted from HOST, generating a plurality of power stress test modules occupying different amounts of logic resources for the dynamic PR region, and the plurality of power stress test modules are served as hardware logic for the dynamic PR region operating in the power test mode.

3. The method according to claim 2 , wherein after generating the plurality of power stress test modules occupying different amounts of logic resources for the dynamic PR region, the method further comprises:
generating dynamic PR profiles of various power stress levels by jointly compiling the plurality of power stress test modules with the static region, wherein
the dynamic PR profiles are burned and cured to the Flash memory in advance, or are burned and cured to the Flash memory upon receiving the request for power stress test.

4. The method according to claim 2 , wherein after generating the plurality of power stress test modules occupying different amounts of logic resources for the dynamic PR region, the method further comprises:
automatically configuring, in response to receiving an instruction for configuring power stress parameters transmitted from HOST, corresponding stress parameters for power stress test modules of the same level, to control a power value of the FPGA acceleration card.

5. The method according to claim 1 , wherein the static region comprises peripheral component interconnect express (PCIe), a double data rate (DDR) driver, an optical module driver, and a reconfiguration module; only a connection interface is reserved between the static region and the dynamic PR region;
wherein the reconfiguration module is configured to cause HOST to load, according to the partial reconfiguration method, the dynamic PR profiles to the dynamic PR region through the PCIe.

6. The method according to claim 5 , wherein setting the operating mode of the dynamic PR region as the power test mode comprises:
in response to a mode adjustment instruction transmitted from the HOST, configuring, through the PCIe, the operating mode of the dynamic PR region as the power test mode.

7. An apparatus for performing a power stress test on a field programmable gate array (FPGA) acceleration card, comprising a processor and a memory, wherein the memory is configured to store a computer program, and the processor is configured to call the computer program stored in the memory and run the computer program to:
divide the FPGA acceleration card into a static region and a dynamic partial reconfiguration (PR) region according to a partial reconfiguration method; and burn FPGA firmware with a partial reconfiguration function to a Flash memory, the static region being a hardware logic implementation region for functional tests other than the power stress test, the dynamic PR region comprising a blank mode occupying no hardware resource and a power test mode for performing the power stress test, wherein the dynamic PR region in the blank mode is used for performing a test other than the power stress test in conjunction with the static region;
in response to receiving a request for power stress test, set an operating mode of the dynamic PR region as the power test mode; and load dynamic PR profiles burned in the Flash memory to the dynamic PR region; and
call power stress test modules to perform the power stress test in the dynamic PR region.

8. The apparatus according to claim 7 , wherein the processor is further configured to:
generate, in response to receiving an instruction for configuring power stress test modules transmitted from HOST, a plurality of power stress test modules occupying different amounts of logic resources for the dynamic PR region, and the plurality of power stress test modules are served as hardware logic for the dynamic PR region operating in the power test mode.

9. A non-transitory computer-readable storage medium storing programs for performing a power stress test on a field programmable gate array (FPGA) acceleration card, wherein the programs for performing the power stress test on the FPGA acceleration card, when executed by a processor, implements steps of:
dividing, according to a partial reconfiguration (PR) method, the FPGA acceleration card into a static region and a dynamic PR region in advance, and burning FPGA firmware with a partial reconfiguration function to a Flash memory;
in response to receiving a request for power stress test, setting an operating mode of the dynamic PR region as a power test mode, and loading dynamic PR profiles burned in the Flash memory to the dynamic PR region; and
calling power stress test modules to perform the power stress test in the dynamic PR region, wherein
the static region is a hardware logic implementation region for a functional test other than the power stress test, the dynamic PR region comprises a blank mode occupying no hardware resource and the power test mode for performing the power stress test, and the dynamic PR region in the blank mode is used for performing a test other than the power stress test in conjunction with the static region.

10. The method according to claim 1 , the burning FPGA firmware with the partial reconfiguration function to the Flash memory comprises:
generating, by jointly compiling the dynamic PR region operating in the blank mode with the static region, FPGA profiles and profiles of the dynamic PR region in the blank mode that are served as the FPGA firmware with the partial reconfiguration function; and
burning and curing the FPGA firmware to the Flash memory.

11. The method according to claim 10 , further comprising:
in response to receiving a request for functional test other than the power stress test, setting the operating mode of the dynamic PR region as the blank mode; and
performing the functional test other than the power stress test in the static region.

12. The method according to claim 1 , wherein the operating mode of the dynamic PR region is set according to an upper-level instruction.

13. The method according to claim 3 , wherein loading dynamic PR profiles burned in the Flash memory to the dynamic PR region comprises loading dynamic PR files of different levels according to power stress test requirements of users.

14. The method according to claim 4 , wherein different stress parameters are configured for power stress test modules of the same level.

15. The method according claim 1 , wherein the par

Assignees

• Inspur Suzhou Intelligent Technology Co Ltd

Inventors

• Zhang Jingdong
• Wang Jiangwei
• Kan Hongwei
• Xu Yaming

Classifications

• G06F11/2221 Primary

  to test input/output devices or peripheral units · CPC title

• G06F11/24 Primary

  Marginal checking {or other specified testing methods not covered by G06F11/26, e.g. race tests} · CPC title

• G06F11/2273

  Test methods · CPC title