Adaptive clock duty-cycle controller

Patent metadata

Field	Value
Publication number	US-11855645-B2
Application number	US-202117485361-A
Country	US
Kind code	B2
Filing date	Sep 25, 2021
Priority date	Sep 25, 2021
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

Aspects of the present disclosure related to a method of duty-cycle distortion compensation in a system including a clock generator configured to generate a clock signal. The method includes measuring one or more parameters of the clock signal, determining a duty-cycle adjustment based on the measured one or more parameters, and adjusting a duty cycle of the clock signal based on the determined duty-cycle adjustment.

First claim

What is claimed is:

1. A system, comprising:
a duty-cycle adjuster having a signal input, a control input, and an output, wherein the duty-cycle adjuster is configured to receive a clock signal at the signal input, receive a control signal at the control input, adjust a duty cycle of the clock signal based on the control signal to generate a duty-cycle adjusted clock signal, and output the duty-cycle adjusted clock signal at the output of the duty-cycle adjuster;
a timing measurement circuit having an input coupled to the output of the duty-cycle adjuster, wherein the timing measurement circuit is configured to receive the duty-cycle adjusted clock signal at the input of the timing measurement circuit, measure one or more parameters of the duty-cycle adjusted clock signal, and generate a measurement signal based on the measured one or more parameters;
a signal path coupled between the output of the duty-cycle adjuster and the input of the timing measurement circuit, the signal path comprising delay buffers coupled in series; and
one or more flip-flops coupled to the signal path.

2. The system of claim 1 , wherein the timing measurement circuit comprises:
a time-to-digital converter (TDC) configured to measure a time delay between a first edge of the duty-cycle adjusted clock signal and a second edge of the duty-cycle adjusted clock signal; and
a measurement control circuit coupled to the TDC, wherein the measurement control circuit is configured to generate the measurement signal based on the measured time delay.

3. The system of claim 2 , wherein the first edge of the duty-cycle adjusted clock signal is a rising edge and the second edge of the duty-cycle adjusted clock signal is a falling edge.

4. The system of claim 2 , wherein the first edge of the duty-cycle adjusted clock signal is a falling edge and the second edge of the duty-cycle adjusted clock signal is a rising edge.

5. The system of claim 1 , wherein the timing measurement circuit further comprises:
a launch circuit configured to launch an edge of a timing signal on a first edge of the duty-cycle adjusted clock signal;
a capture circuit configured to output an edge of a capture signal on a second edge of the duty-cycle adjusted clock signal;
a time-to-digital converter (TDC) having a signal input and a capture input, wherein the signal input of the TDC is configured to receive the timing signal, the capture input of the TDC is configured to receive the capture signal, and the TDC is configured to measure a time delay between a time that the edge of the timing signal is received and a time that the edge of the capture signal is received; and
a measurement control circuit coupled to the TDC, wherein the measurement control circuit is configured to generate the measurement signal based on the measured time delay.

6. The system of claim 5 , wherein the TDC comprises:
a flip-flop having a signal input, a clock input, and an output, wherein the signal input of the flip-flop is coupled to the signal input of the TDC, the clock input of the flip-flop is coupled to the capture input of the TDC, and the output of the flip-flop is coupled to an output of the TDC.

7. The system of claim 5 , wherein the TDC comprises:
a delay line coupled to the signal input of the TDC, the delay line comprising delay buffers coupled in series; and
flip-flops, each of the flip-flops having a respective signal input, a respective clock input, and a respective output, wherein the signal input of each of the flip-flops is coupled to an output of a respective one of the delay buffers in the delay line, and the clock input of each of the flip-flops is coupled to the capture input of the TDC.

8. The system of claim 1 , wherein the duty-cycle adjuster is configured to:
generate multiple delayed versions of the clock signal; and
combine high phases of the multiple delayed versions of the clock signal or combine low phases of the multiple delayed versions of the clock signal.

9. The system of claim 8 , wherein the multiple delayed versions of the clock signal overlap in time.

10. The system of claim 8 , wherein the duty-cycle adjuster is configured to set a number of the multiple delayed versions of the clock signal that are generated based on the control signal.

11. The system of claim 1 , further comprising a duty-cycle control circuit coupled to the duty-cycle adjustment and the timing measurement circuit, wherein the duty-cycle control circuit is configured to receive the measurement signal from the timing measurement circuit and generate the control signal based on the measurement signal.

12. The system of claim 11 , wherein the one or more parameters include one or more of a high phase of the duty-cycle adjusted clock signal, a low phase of the duty-cycle adjusted clock signal, and a period of the duty-cycle adjusted clock signal.

13. The system of claim 12 , wherein:
the measurement signal indicates the high phase of the duty-cycle adjusted clock signal; and
the duty-cycle control circuit is configured to:
compare the high phase of the duty-cycle adjusted clock signal with a target high phase; and
generate the control signal based on the comparison.

14. The system of claim 12 , wherein:
the measurement signal indicates the low phase of the duty-cycle adjusted clock signal; and
the duty-cycle control circuit is configured to:
compare the low phase of the duty-cycle adjusted clock signal with a target low phase; and
generate the control signal based on the comparison.

15. The system of claim 12 , wherein:
the measurement signal indicates the high phase of the duty-cycle adjusted clock signal and the low phase of the duty-cycle adjusted clock signal; and
the duty-cycle control circuit is configured to:
compare the high phase of the duty-cycle adjusted clock signal with the low phase of the duty-cycle adjusted clock signal; and
generate the control signal based on the comparison.

16. A method of duty-cycle distortion compensation in a system including a clock generator configured to generate a clock signal, a circuit, and a signal path coupled between the clock generator and the circuit, the method comprising:
measuring one or more parameters of the clock signal at a first node between the signal path and the circuit;
determining a duty-cycle adjustment based on the measured one or more parameters; and
adjusting a duty cycle of the clock signal at a second node between the clock generator and the signal path based on the determined duty-cycle adjustment, wherein the signal path comprises delay buffers coupled in series, wherein the circuit comprises one or more flip-flops.

17. The method of claim 16 , wherein the one or more parameters include one or more of a high phase of the clock signal, a low phase of the clock signal, and a period of the clock signal.

18. The method of claim 17 , wherein the one or more parameters includes the high phase of the clock signal, and determining the duty-cycle adjustment comprises:
comparing the high phase of the clock signal with a target high phase; and
determining the duty-cycle adjustment based on the comparison.

19. The method of claim 17 , wherein the one or more parameters includes the low phase of the clock signal, and determining the duty-cycle adjustment comprises:
comparing the low phase of the clock signal with a target low phase; and
determining the duty-cycle adjustment based on the comparison.

20. The method of claim 17 , wherein the one or more parameters includes the high phase of the

Assignees

• Qualcomm Inc

Inventors

• Bowman Keith Alan
• Yingling Daniel
• Pal Dipti Ranjan

Classifications

• H03K5/1565 Primary

  the output pulses having a constant duty cycle · CPC title

• H03K3/017

  Adjustment of width or dutycycle of pulses (pulse width modulation H03K7/08 {; to maintain energy constant H03K3/015}) · CPC title

• H03L7/0814

  the phase shifting device being digitally controlled · CPC title