Semiconductor device

Patent metadata

Field	Value
Publication number	US-11855135-B2
Application number	US-202117508259-A
Country	US
Kind code	B2
Filing date	Oct 22, 2021
Priority date	Oct 23, 2020
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

An object of the disclosure is to provide a semiconductor device having enhanced adhesion of the electrode while improving the reverse direction breakdown voltage, which is especially useful for power devices. A semiconductor device including a semiconductor layer and an electrode layer provided on the semiconductor layer and including at least a first electrode layer and a second electrode layer provided on the first electrode layer, wherein an outer edge portion of the second electrode layer is located outside an outer edge portion of the first electrode layer, wherein the semiconductor layer includes an electric field relaxation region with a different electrical resistivity from that of the semiconductor layer, and wherein the electric field relaxation region overlaps at least a part of a portion of the second electrode layer located outside the outer edge portion of the first electrode layer in plan view.

First claim

The invention claimed is:

1. A semiconductor device comprising:
a semiconductor layer; and
an electrode layer provided on the semiconductor layer and including a first electrode layer and a second electrode layer provided on the first electrode layer,
wherein an outer edge portion of the second electrode layer is located outside an outer edge portion of the first electrode layer,
wherein the semiconductor layer includes an electric field relaxation region with a different electrical resistivity from the semiconductor layer, and
wherein the electric field relaxation region overlaps at least a part of a portion of the second electrode layer located outside the outer edge portion of the first electrode layer in a plan view.

2. The semiconductor device according to claim 1 , wherein the semiconductor layer includes a crystalline oxide semiconductor as a main component.

3. The semiconductor device according to claim 2 , wherein the crystalline oxide semiconductor contains one or more metals selected from aluminum, indium and gallium.

4. The semiconductor device according to claim 2 , wherein the crystalline oxide semiconductor contains at least gallium.

5. The semiconductor device according to claim 3 , wherein the crystalline oxide semiconductor has a corundum structure or a ß-gallia structure.

6. The semiconductor device according to claim 1 , wherein a work function of the first electrode layer is greater than a work function of the second electrode layer.

7. The semiconductor device according to claim 1 , wherein the electric field relaxation region and an outer edge portion of the second electrode layer overlap in a plan view.

8. The semiconductor device according to claim 1 , wherein the semiconductor layer has an uneven portion on at least a part of a surface of the semiconductor layer located outside the outer edge portion of the first electrode layer.

9. The semiconductor device according to claim 1 , wherein the semiconductor layer has an uneven portion on at least a part of a surface of the semiconductor layer located at an outer edge portion of the second electrode layer.

10. The semiconductor device according to claim 8 , wherein the uneven portion includes a trench.

11. The semiconductor device according to claim 1 , further comprising a passivation film covering an interface between the outer edge portion of the second electrode layer and the semiconductor layer.

12. The semiconductor device according to claim 1 , wherein an insulator layer is provided between the semiconductor layer and the electrode layer.

13. The semiconductor device according to claim 12 , wherein at least a portion of the electric field relaxation region overlaps with an inner edge portion of the insulator layer in a plan view.

14. The semiconductor device according to claim 12 , wherein the insulator layer has an uneven portion at an interface between the second electrode layer and the insulator layer.

15. The semiconductor device according to claim 14 , wherein the uneven portion of the insulator layer includes a trench.

16. The semiconductor device according to claim 15 , wherein the electric field relaxation region has a portion overlapping with the trench in a plan view.

17. The semiconductor device according to claim 12 , further comprising a passivation film covering an interface between an outer edge portion of the second electrode layer and the insulator layer.

18. The semiconductor device according to claim 1 , wherein the semiconductor device includes a diode or a transistor.

19. The semiconductor device according to claim 1 , wherein the semiconductor device includes a power device.

20. A power converter employing the semiconductor device according to claim 1 .

21. A control system employing the semiconductor device according to claim 1 .

Assignees

• Flosfia Inc

Inventors

• Okigawa Mitsuru
• Yanagida Hideaki
• Shinohe Takashi

Classifications

• H10P14/24

  using chemical vapour deposition [CVD] · CPC title

• H10P14/265

  using solutions · CPC title

• H10P14/3434

  being oxide semiconductor materials (Group IIB-VIA semiconductor materials H10P14/3424) · CPC title

• H10P14/3234

  being oxide semiconducting materials (Group IIB-VIA semiconductors H10P14/3224) · CPC title

• H10D99/00

  Subject matter not provided for in other groups of this subclass · CPC title