Semiconductor storage device and manufacturing method thereof

US11854971B2 · US · B2

Patent metadata
FieldValue
Publication numberUS-11854971-B2
Application numberUS-202117190713-A
CountryUS
Kind codeB2
Filing dateMar 3, 2021
Priority dateMay 19, 2020
Publication dateDec 26, 2023
Grant dateDec 26, 2023

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  1. Title

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  2. Abstract

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  3. Assignees and inventors

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  4. Key dates

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  5. First independent claim

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  6. CPC / IPC classifications

    Technology tags used to group this patent with similar filings.

  7. Citations and related patents

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Abstract

Official abstract text for this publication.

A semiconductor storage device includes: conductive layers arranged in a first direction; a first insulating layer extending in the first direction; a first semiconductor layer between the conductive layers and the first insulating layer; and a gate insulating film between the conductive layers and the first semiconductor layer. The first semiconductor layer includes a first region between a first insulating portion and the first conductive layer, a second region between a second insulating portion and the second conductive layer, and a third region between the first region and the second region. The third region includes a fourth region extending in a second direction, a fifth region between the first region and the fourth region, a sixth region between the second region and the fourth region, and a seventh region between the fifth region and the first region and extending in the first direction.

First claim

Opening claim text (preview).

What is claimed is: 1. A semiconductor storage device comprising: a substrate; a plurality of conductive layers arranged in a first direction intersecting with a surface of the substrate; a first insulating layer extending in the first direction; a first semiconductor layer provided between the plurality of conductive layers and the first insulating layer; and a gate insulating film provided between the plurality of conductive layers and the first semiconductor layer, wherein a cross-section, extending in the first direction and a second direction intersecting with the first direction, in part includes a first one and a second one of the plurality of conductive layers that are adjacent to each other in the first direction, the first insulating layer, the first semiconductor layer, and the gate insulating film, the first insulating layer includes: a first insulating portion having a first width in the second direction, and a second insulating portion that has a second width smaller than the first width in the second direction, and is separated from the first insulating portion in the first direction, and the first semiconductor layer includes a first region provided between the first insulating portion and the first conductive layer, a second region provided between the second insulating portion and the second conductive layer, and a third region provided between the first region and the second region, the third region includes a fourth region extending in the second direction, a fifth region provided between the first region and the fourth region, a sixth region provided between the second region and the fourth region, and a seventh region provided between the fifth region and the first region and extending in the first direction, the first region of the first semiconductor layer has a first thickness from a surface on a side of the first insulating layer to the gate insulating film, the second region of the first semiconductor layer has a second thickness from a surface on the side of the first insulating layer to the gate insulating film, the seventh region of the first semiconductor layer has a third thickness from a surface on the side of the first insulating layer to the gate insulating film, a surface in the fifth region on the side of the first insulating layer includes a region with a shortest distance to the gate insulating film larger than the first thickness, the second thickness, and the third thickness, and a shortest distance to the gate insulating film from a surface in the sixth region on the side of the first insulating layer is larger than the first thickness minus 2 nm and is larger than the second thickness minus 2 nm. 2. The semiconductor storage device according to claim 1 , wherein in the cross-section, a shortest distance to the gate insulating film from a surface in the third region on the side of the first insulating layer is equal to one of the first thickness or the second thickness. 3. The semiconductor storage device according to claim 1 , wherein in the cross-section, a shortest distance to the gate insulating film from the surface in the sixth region on the side of the first insulating layer is equal to one of the first thickness or the second thickness. 4. The semiconductor storage device according to claim 1 , wherein in the cross-section, a surface in the seventh region on the side of the first insulating layer includes a region with a shortest distance to the gate insulating film. 5. The semiconductor storage device according to claim 4 , wherein in the cross-section, the shortest distance to the gate insulating film from the surface in the seventh region on the side of the first insulating layer is larger than the first thickness minus 2 nm, and larger than the second thickness minus 2 nm. 6. The semiconductor storage device according to claim 5 , wherein in the cross-section, the shortest distance to the gate insulating film from the surface in the seventh region on the side of the first insulating layer is equal to one of the first thickness or the second thickness. 7. The semiconductor storage device according to claim 4 , further comprising: a second semiconductor layer provided between the substrate and the first semiconductor layer, and connected to the substrate and the first semiconductor layer, wherein the seventh region is connected to the second semiconductor layer.

Assignees

Inventors

Classifications

  • the openings being tapered via holes · CPC title

  • Vias, e.g. via plugs · CPC title

  • H10W20/435Primary

    Cross-sectional shapes or dispositions of interconnections · CPC title

  • Electricity · mapped topic

  • Electricity · mapped topic

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Frequently asked questions

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What does patent US11854971B2 cover?
A semiconductor storage device includes: conductive layers arranged in a first direction; a first insulating layer extending in the first direction; a first semiconductor layer between the conductive layers and the first insulating layer; and a gate insulating film between the conductive layers and the first semiconductor layer. The first semiconductor layer includes a first region between a fi…
Who is the assignee on this patent?
Kioxia Corp
What technology area does this patent fall under?
Primary CPC classification H10W20/435. Mapped technology areas include Electricity.
When was this patent published?
Publication date Tue Dec 26 2023 00:00:00 GMT+0000 (Coordinated Universal Time) (B2). Legal status and post-grant events are not shown on this page.
What related patents are in patentsdb?
We list 12 related publications on this page (citations in our corpus or others sharing the same primary CPC).