Memory system storage device with power loss protection circuit

Patent metadata

Field	Value
Publication number	US-11854645-B2
Application number	US-202217694946-A
Country	US
Kind code	B2
Filing date	Mar 15, 2022
Priority date	Sep 9, 2019
Publication date	Dec 26, 2023
Grant date	Dec 26, 2023

Abstract

A memory system and storage device are provided, including: an auxiliary power device having at least one capacitor, wherein the at least one capacitor has a first path for leakage current; a charging circuit including a switch connected to the auxiliary power device; and a state determining circuit connected to the auxiliary power device, wherein the state determining circuit includes a path circuit connected in parallel with the at least one capacitor to form a second path having at least one of a resistance lower than a resistance of the first path or a current source.

First claim

What is claimed is:

1. A storage device comprising:
a power loss protection (PLP) circuit;
an auxiliary power device circuit, including at least one capacitor, wherein the at least one capacitor has a first path for leakage current; and
a main system including a controller and a plurality of memory devices,
wherein the PLP circuit is connected to the auxiliary power device circuit, includes a charging circuit including a switch, and includes a state determining circuit,
wherein the state determining circuit includes a path circuit connected in parallel with the at least one capacitor to form a second path having a resistance lower than a resistance of the first path, and
wherein the state determining circuit is configured to determine an abnormal state as an open state if a time of an off period of the switch is shorter than a time of a preset first period when a voltage of the at least one capacitor aperiodically cycles between a first voltage level and a second voltage level.

2. The storage device of claim 1 , wherein:
the charging circuit comprises a direct current (DC)-DC converter.

3. The storage device of claim 1 , wherein the state determining circuit is further configured to:
measure the voltage of the at least one capacitor and determine a fault of the at least one capacitor by comparing a change time of the measured voltage with a reference time;
determine a state of the auxiliary power device circuit to be in a normal state, when the voltage of the at least one capacitor periodically cycles between the first voltage level and the second voltage level that is lower than the first voltage level; and
determine the state of the auxiliary power device circuit to be in the abnormal state, when the voltage of the at least one capacitor aperiodically cycles or deviates from between the first voltage level and the second voltage level.

4. The storage device of claim 3 , wherein:
the state determining circuit is further configured to determine the abnormal state as a short state if the voltage of the at least one capacitor is measured as being lower than or equal to a third voltage level that is lower than the second voltage level.

5. The storage device of claim 1 , wherein:
the path circuit comprises a resistor, and
a first current flowing through the first path is less than a second current flowing through the resistor.

6. The storage device of claim 1 , wherein:
the second path comprises a variable resistor, and
the variable resistor is variably adjusted based on a change of resistance in an insulating resistor of the first path of the at least one capacitor.

7. The storage device of claim 1 , wherein:
the path circuit comprises a first resistor and a second resistor that are connected in series to form the second path, and is configured to feed back a feedback voltage to the charging circuit through a node to which the first resistor and the second resistor are connected to maintain substantially constant a voltage applied to the at least one capacitor.

8. The storage device of claim 1 , wherein:
the state determining circuit further comprises a third path for leakage current in addition to the first path and the second path.

9. The storage device of claim 1 , wherein:
the auxiliary power device circuit comprises a plurality of capacitors, and
each of the plurality of capacitors is connected to at least one other of the plurality of capacitors in at least one of a serial manner, a parallel manner, or a combination of the serial manner and the parallel manner.

10. The storage device of claim 1 , wherein:
the auxiliary power device circuit comprises a plurality of capacitors connected in parallel,
the charging circuit comprises at least one field effect transistor (FET) in the switch and a direct current (DC)-DC converter,
the state determining circuit is configured to determine a state of the auxiliary power device circuit by measuring a time of at least one of an off period of the at least one FET or an on period of the at least one FET and comparing the measured time with a reference time, and
the path circuit is connected in parallel with the plurality of capacitors to form the second path having a resistance value that is less than a resistance value of the first path.

11. The storage device of claim 1 , wherein:
the charging circuit is configured to apply a voltage to the at least one capacitor, and
the state determining circuit is configured to measure a voltage of a charge/discharge period of the at least one capacitor and determine a fault of the at least one capacitor by comparing a measured time of the charge/discharge period with a reference time.

12. A storage device comprising:
a power loss protection (PLP) circuit;
an auxiliary power device circuit including at least one capacitor, wherein the at least one capacitor has a first path for leakage current; and
a main system including a controller and a plurality of memory devices,
wherein the PLP circuit is connected to the auxiliary power device circuit, includes a charging circuit including a switch, and includes a state determining circuit,
wherein the state determining circuit includes:
a path circuit connected in parallel with the at least one capacitor to form a second path having at least one of a resistance lower than a resistance of the first path or a current source; and
another path circuit, connected in parallel with the first path and the second path, to form a third path for the leakage current, and

wherein the state determining circuit is configured to:
determine a state of the auxiliary power device circuit to be in a normal state if a voltage of the at least one capacitor periodically cycles between a first voltage level and a second voltage level that is lower than the first voltage level;
determine the auxiliary power device circuit to be in an open state if a time of an off period of the switch is shorter than a time of a preset first period, when the voltage of the at least one capacitor aperiodically cycles between the first voltage level and the second voltage level that is lower than the first voltage level; and
determine the auxiliary power device circuit to be in a short state if the voltage of the at least one capacitor is measured as being lower than or equal to a third voltage level that is lower than the second voltage level.

13. The storage device of claim 12 ,
wherein the second path is coupled to a current measurement circuit configured to measure voltages of the at least one capacitor, and
wherein the current measurement circuit is coupled to a detection circuit configured to detect a fault of the at least one capacitor by comparing a change time of the measured voltage with a reference time.

14. The storage device of claim 12 ,
wherein the open state is an electrical open type of abnormal state,
wherein the short state is an electrical short type of abnormal state, and
wherein the second path has an impedance lower than an impedance of the first path.

15. The storage device of claim 12 , wherein:
the third path comprises at least one resistor, and
a current flowing through the first path is less than another current flowing through the at least one resistor.

16. The storage device of claim 12 , wherein:
the auxiliary power device circuit comprises a plurality of capacitors, and
each of the plurality of capacitors is connected to at least one other of the plurality of capacitors in at least one of a serial manner, a parallel manner, or a combination of the serial manner and the parallel manner.

17. A me

Assignees

• Samsung Electronics Co Ltd

Inventors

• Lee Woosung
• Ryu Chunghyun
• Lim Hyoungtaek

Classifications

• H02J7/933

  the cycle being controlled or terminated in response to electric parameters · CPC title

• G11C5/005 Primary

  Circuit means for protection against loss of information of semiconductor storage devices · CPC title

• G11C5/141 Primary

  Battery and back-up supplies · CPC title

• G11C5/148 Primary

  Details of power up or power down circuits, standby circuits or recovery circuits · CPC title

• G01R31/36 Primary

  Arrangements for testing, measuring or monitoring the electrical condition of accumulators or electric batteries, e.g. capacity or state of charge [SoC] · CPC title